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this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this pr oposed product without notice. publication number s29cd-g_00 revision b amendment 0 issue date november 14, 2005 s29cd-g flash family s29cd032g, s29cd016g 32 megabit (1m x 32-bit), 16 megabit (512k x 32-bit) 2.5 volt-only burst mode, dual boot, simultaneous read/ write flash memory with versa tilei/o? featuring 170 nm process technology data sheet preliminary notice to readers: this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. du e to the phases of the manufacturing process that require maintaining efficien cy and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. note: this document supercedes datasheet information for the s29cd016g revision a4, and s29cd032g revision b0. the s29cd-g device is the factory-recommended migration path. please refer to specifications and ordering information found in this document.
ii s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary notice on data sheet designations spansion llc issues data sheets with advance information or preliminary designations to advise readers of product information or intended specif ications throughout the product life cycle, includ- ing development, qualification, initial production , and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de- sign. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe- cific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the prod- uct may discontinue. spansion llc therefore pl aces the following conditions upon advance information content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con - tacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the pr oduct development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initia l production, and the subsequent phases in the manufacturing process that occur before full prod uction is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as- pects of production under consideration. span sion places the following conditions upon preliminary content: ?this document states the current technical specific ations regarding the spansion product(s) described herein. the preliminary status of this document indi cates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revise d by subsequent versions or modifica - tions due to changes in technical specifications.? combination some data sheets will contain a combination of products with different designations (advance in- formation, preliminary, or full production). this type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with dc charac teristics table and ac erase and program table (in the table notes). the disclaimer on the first page refe rs the reader to the notice on this page. full production (no desi gnation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designat ion is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option , temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incor- rect specification. spansion llc applies the follo wing conditions to documents in this category: ?this document states the current technical specific ations regarding the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that sub - sequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
publication number s29cd-g_00 revision b amendment 0 issue date november 14, 2005 preliminary this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this pr oposed product without notice. s29cd-g flash family s29cd032g, s29cd016g 32 megabit (1m x 32-bit), 16 megabit (512k x 32-bit) 2.5 volt-only burst mode, dual boot, simultaneous read/ write flash memory with versatilei/o? featuring 170 nm process technology data sheet distinctive characteristics architecture advantages ? simultaneous read/write operations ? read data from one bank while executing erase/ program functions in other bank ? zero latency between read and write operations ? two bank architecture: large bank/small bank 75%/25% ? user-defined x32 data bus ? dual boot block ? top and bottom boot sect ors in the same device ? flexible sector architecture ? cd032g: eight 2k double word, sixty-two 16k double word, and eight 2k double word sectors ? cd016g: eight 2k double word, thirty-two 16k double word, and eight 2k double word sectors ? secured silicon sector (256 bytes) ? factory locked and identifiabl e: 16 bytes for secure, random factory electronic serial number; also know as electronic marking ? manufactured on 170 nm process technology ? programmable burst interface ? interfaces to any high performance processor ? linear burst read operatio n: 2, 4, and 8 double word linear burst with or without wrap around ? program operation ? performs synchronous an d asynchronous write operations of burst config uration register settings independently ? single power supply operation ? optimized for 2.5 to 2.75 volt read, erase, and program operations ? compatibility with jedec standards (jc42.4) ? software compatible with single-power supply flash ? backward-compatible wi th amd/fujitsu am29lv/ mbm29lv and am29f/mbm29f flash memories performance characteristics ? high performance read access ? initial/random access times of 48 ns (32 mb) and 54 ns (16 mb) ? burst access times of 7.5 ns (32 mb) or 9 ns (16mb) ? ultra low power consumption ? burst mode read: 90 ma @ 75 mhz max ? program/erase: 50 ma max ? standby mode: cmos: 60 a max ? 1 million write cycles per sector typical ? 20 year data retention typical ? versatilei/o? control ? generates data output vo ltages and tolerates data input voltages as determined by the voltage on the v io pin ? 1.65 v to 3.60 v compatible i/o signals software features ? persistent sector protection ? locks combinations of individual sectors and sector groups to prevent program or erase operations within that sector (requires only v cc levels) ? password sector protection ? locks combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-definable 64-bit password ? supports common flash interface (cfi) ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ? data# polling and toggle bits ? provides a software method of detecting program or erase operation completion hardware features ? program suspend/resume & erase suspend/ resume ? suspends program or erase operations to allow reading, programming, or erasing in same bank ? hardware reset (reset#), ready/busy# (ry/ by#), and write protect (wp#) inputs ? acc input ? accelerates programming ti me for higher throughput during system production ? package options ?80-pin pqfp ? 80-ball fortified bga ? pb-free package option also available ? known good die
2s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary general description the s29cd-g flash family is a burst mode, dual b oot, simultaneous read/write family of flash memory with versatilei/o? manufactured on 170 nm process technology. the s29cd032g is a 32 megabit, 2.6 volt-only (2.50 v - 2.75 v) single power supply burst mode flash memory device that can be co nfigured for 1,048,576 double words. the s29cd016g is a 16 megabit, 2.6 volt-only (2.50 v - 2.75 v) single power supply burst mode flash memory device that can be co nfigured for 524,288 double words. to eliminate bus contention, each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. additional control inputs are required for synchronous burst oper- ations: load burst address valid (adv#), and clock (clk). each device requires only a single 2.6 volt-only (2.50 v ? 2.75 v) for both read and write func- tions. a 12.0-volt v pp is not required for program or erase operations, although an acceleration pin is available if faster programming performance is required. the device is entirely command set compatible with the jedec single-power-supply flash stan- dard. the software command set is compatible with the command sets of the 5 v am29f or mbm29f and 3 v am29lv or mbm29lv flash fa milies. commands are wr itten to the command register using standard microprocessor write timing. register contents serve as inputs to an in- ternal state-machine that cont rols the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into two banks. the device can begin programming or erasing in one bank, and then simultaneously read from the other bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. see simultaneous read/write opera- tions overview . the device provides a 256-byte secured silicon sector that contains electronic marking infor- mation for easy device traceability. in addition, the device features several levels of sector protection, which can disable both the pro- gram and erase operations in certain sectors or sector groups: persistent sector protection is a command sector protection method that replac es the old 12 v controlled protection method; password sector protection is a highly sophisticated protection method that requires a pass- word before changes to certain sectors or sector groups are permitted; wp# hardware protection prevents program or erase in the two oute rmost 8 kbytes sectors of the larger bank. the device defaults to the persistent sector protection mode. the customer must then choose if the standard or password protection method is most desirable. the wp# hardware protection feature is always available, independent of the other protection method chosen. the versatilei/o? (v ccq ) feature allows the output voltage generated on the device to be de- termined based on the v io level. this feature allows this device to operate in the 1.8 v i/o environment, driving and receiving signals to and from other 1.8 v devices on the same bus. the host system can detect whether a program or erase operation is complete by observing the ry/by# pin, by reading the dq7 (d ata# polling), or dq6 (toggle) status bits . after a program or erase cycle is completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory.
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 3 preliminary hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the password and software sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system at v cc level. the program/erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or prog ram data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the device offers two power-savi ng features. when addresses are stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunnelling. the data is programmed using hot electron injection.
4s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 block diagram of simultaneous read/write circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 prq080?80-lead plastic quad flat package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 special package handling instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 laa080?80-ball fortified ball grid array (13 x 11 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 s29cd032g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 s29cd016g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 memory map and sector protect groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 device operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 versatilei/o? (v io ) control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 requirements for reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 simultaneous read/write operations overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 overview ...................................................................................................................... ..................................................................24 program/erase suspend and simultaneous operation .............................................................................. .......................24 common flash interface (cfi) and passwo rd program/verify and simultaneous operation .............................24 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 accelerated program and erase operations ...................................................................................... .................................25 autoselect functions .......................................................................................................... .........................................................25 automatic sleep mode (asm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 standby mode .................................................................................................................. ..............................................................25 reset#: hardware reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 asynchronous read operation (non-burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 synchronous (burst) read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 linear burst read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ce# control in linear mode .................................................................................................... .............................................. 28 adv# control in linear mode ................................................................................................... ........................................... 28 reset# control in linear mode ................................................................................................. ........................................... 29 oe# control in linear mode .................................................................................................... .............................................. 29 ind/wait# operation in linear mode ............................................................................................ .................................. 29 burst access timing control ................................................................................................... ................................................30 initial burst access delay control ............................................................................................ .............................................30 burst clk edge data delivery .................................................................................................. ..............................................30 burst data hold control ....................................................................................................... ....................................................30 asserting reset# during a burst access ........................................................................................ ....................................31 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 initial access delay configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 sector and sector groups ...................................................................................................... ................................................... 33 persistent sector protection .................................................................................................. .................................................. 33 password sector protection .................................................................................................... ................................................. 33 wp# hardware protection ....................................................................................................... ............................................... 33 persistent sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 persistent protection bit (ppb) ............................................................................................... .................................................34 persistent protection bit lock (ppb lock) ................. .................................................................... .....................................34 dynamic protection bit (dyb) .................................................................................................. ..............................................34 persistent sector protection mode locking bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 5 preliminary password protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 password and password mode locking bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 64-bit password ............................................................................................................... .............................................................36 write protect (wp#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 secured silicon otp sector and simultaneous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 persistent protection bit lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 low v cc write inhibit ................................................................................................................ ...............................................37 write pulse glitch protection ................................................................................................................... ................................38 logical inhibit ............................................................................................................... ..................................................................38 power-up write inhibit ........................................................................................................ .....................................................38 v cc and v io power-up and power-down sequencing ........................................................................................... .........38 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 reading array data in non-burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 reading array data in burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 read/reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 autoselect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 program command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 accelerated program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 unlock bypass command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 unlock bypass entry command ................................................................................................... ...........................................45 unlock bypass program command ................................................................................................. .......................................45 unlock bypass chip erase command .............................................................................................. .................................... 46 unlock bypass cfi command ..................................................................................................... ............................................ 46 unlock bypass reset command ................................................................................................... .......................................... 46 chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 sector erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 sector erase and program suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 sector erase and program suspend operation mechanics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 sector erase and program resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 configuration register read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 configuration register write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 common flash interface (cfi) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 password program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 password verify command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 password protection mode locking bit program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 persistent sector protection mode locking bit program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ppb lock bit set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 dyb write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 password unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ppb program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 all ppb erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 dyb write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ppb lock bit set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 dyb status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 ppb status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 ppb lock bit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 non-volatile protection bit program and erase flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ry/by#: ready/busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary dq3: sector erase timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 industrial (i) devices ........................................................................................................ ...........................................................63 extended (e) devices .......................................................................................................... ........................................................63 v cc supply voltages .............................................................................................................. ......................................................63 v io supply voltages .............................................................................................................. .......................................................63 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 zero power flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 vcc and vio power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 asynchronous read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 burst mode read for 32 mb & 16 mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 alternate ce# controlled erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 latchup characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 pqfp and fortified bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 revision summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 7 preliminary ta b l e s table 1. 32 mb memory map and sector prot ect groups for ordering option 00, top boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 2. 32 mb memory map and sector protect groups for ordering option 01, bottom boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 3. 16 mb, memory map and sector protect groups for ordering option 00, top boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4. 16 mb, memory map and sector protect groups for ordering option 00, bottom boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 5. device bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 6. allowable conditions for simultaneous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7. s29cd-g flash family autoselect codes (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 8. 32- bit linear and burst data order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 9. valid configuration regi ster bit definition for ind/wait#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 10. burst initial access delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 11. configuration register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 12. configuration register after device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. sector protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 15. cfi system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 16. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 17. cfi primary vendor-specific extended query. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18. allowed operations during erase/ program suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 19. memory array command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 20. sector protection command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 21. write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 22. test specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
8s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary figures figure 1. asynchronous read operation ........................................................................................... ................................................................................. 27 figure 2. end of burst indicator (ind/wait#) timing for linear 8-word burst operation ........................................... ................................ 29 figure 3. initial burst delay control ........................................................................................... .......................................................................................... 30 figure 4. program operation ..................................................................................................... ............................................................................................. 45 figure 5. erase operation ....................................................................................................... .................................................................................................48 figure 6. data# polling algorithm............................................................................................... ........................................................................................... 57 figure 7. toggle bit algorithm .................................................................................................. ..............................................................................................60 figure 8. maximum negative overshoot waveform ................................................................................... ................................................................... 62 figure 9. maximum positive overshoot waveform................................................................................... ...................................................................... 62 figure 10. i cc1 current vs. time (showing active and automatic sl eep currents)................................................................ ................................ 65 figure 11. typical i cc1 vs. frequency ................................................................................................................. ..................................................................... 65 figure 12. test setup........................................................................................................... ......................................................................................................... 66 figure 13. input waveforms and measurement levels ............................................................................... ...................................................................... 66 figure 14. v cc and v io power-up diagram.............................................................................................................. ............................................................ 67 figure 15. conventional read operations timings................................................................................. ...........................................................................68 figure 16. burst mode read...................................................................................................... ................................................................................................. 70 figure 17. asynchronous command write timing.................................................................................... ........................................................................ 70 figure 18. synchronous command write/read timing ................................................................................ ..................................................................... 71 figure 19. reset# timings....................................................................................................... .................................................................................................. 72 figure 20. wp# timing........................................................................................................... ..................................................................................................... 72 figure 21. chip/sector erase operation timings.................................................................................. .............................................................................. 74 figure 22. back-to-back cycle timings ........................................................................................... ....................................................................................... 74 figure 23. data# polling timings (during embedded al gorithms) ................................................................... ............................................................. 75 figure 24. toggle bit timings (during embedded algo rithms)...................................................................... ................................................................. 75 figure 25. dq2 vs. dq6 for erase/erase suspend operations ....................................................................... ............................................................... 76 figure 26. synchronous data polling timing/toggle bit timings................................................................... ................................................................. 76 figure 27. sector protect/unprotect timing diagram .............................................................................. ........................................................................ 77 figure 28. alternate ce# controlled write operation timings..................................................................... .............................................................. 78
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 9 preliminary product selector guide part number s29cd-g flash family (s29cd032g, s29cd016g) standard voltage range: v cc = 2.5 ? 2.75 v v io = 1.65 ? 2.75 v synchronous/burst or asynchronous speed option (clock rate) 0r (75 mhz) (32 mb only) 0p (66 mhz) 0m (56 mhz) 0j (40 mhz) max initial/asynchronous access time, ns (t acc ) 48 54 64 67 max burst access delay (ns) 7.5 fbga 9 fbga/ 9.5 pqfp 10 fbga/ 10 pqfp 17 max clock rate (mhz) 75 66 56 40 min initial clock delay (clock cycles) 3 3 3 2 max ce# access, ns (t ce ) 52 58 69 71 max oe# access, ns (t oe ) 20 28
10 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to co nfirm availability of specific valid combinations and to ch eck on newly releas ed combinations. 1. the ordering part number that appears on bga packages omits the leading ?s29?. 2. contact your local sales representative for gt grade options. 3. refer to the kgd data sheet supplement for die/wafer sales. s29cd032g 0j f a i 0 0 0 packing type 0 = tray 2 = 7? tape and reel 3 = 13? tape and reel additional ordering options (16th character) top or bottom boot 0=top boot 1 = bottom boot additional ordering options (15th character) mask revision 0 = a 1 = a1 (16 mb only) with 7e, 36, 01/00 autoselect id 2 = a1 (16 mb only) with 7e, 08, 01/00 autoselect id temperature range and quality grade a = industrial (?40c to +85c), gt grade i = industrial (?40c to +85c) m = extended (?40c to +125c), gt grade n = extended (?40c to +125c) material set a=standard f=pb-free option package type q = plastic quad flat package (pqfp) f = fortified ball grid array, 1.0 mm pitch package clock frequency 0j = 40 mhz 0m = 56 mhz 0p = 66 mhz 0r = 75 mhz (32 mb only) device number/description s29cd032g/s29cd016g 32 or 16 megabit (1 m or 512 k x 32-bit) cmos 2.5 volt-only burst mode, dual boot, simultaneous read/write flash memory manufactured on 110 nm floating gate technology valid combinations s29cd032g s29cd016g 0r (32 mb only), 0p, 0m, 0j qai, qfi, qan, qfn 00, 01 fai, ffi, fan, ffn
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 11 preliminary block diagram note: address bus is a19?a0 for 32 mb device, a 18?a0 for 16 mb device. data bus is d31?dq0. input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# reset# acc wp# word# ce# oe# dq max ? dq0 a max ?a0 data latch y-gating cell matrix address latch dq max ?dq0 a max ?a0 burst state control burst address counter adv# clk a max ?a0 v io ind/ wait#
12 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary block diagram of simultaneous read/write circuit note: address bus is a19?a0 for 32 mb device, a 18?a0 for 16 mb device. data bus is d31?dq0. v cc v ss upper bank address reset# we# ce# adv# state control & command register upper bank x-decoder y-decoder latches and control logic oe# dq max ?dq0 dq max ?dq0 lower bank y-decoder x-decoder latches and control logic lower bank address status control a max ?a0 a max ?a0 a max ?a0 a max ?a0 a max ?a0 dq max ?dq0 dq max ?dq0
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 13 preliminary connection diagrams note: on 16 mb device, pin 44 (a19) is nc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 dq16 dq17 dq18 dq19 v ccq v ss dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 v ccq v ss dq28 dq29 dq30 dq31 mch a0 a1 a2 dq15 dq14 dq13 dq12 v ss v ccq dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 v ss v ccq dq3 dq2 dq1 dq0 a19 (32 mb) / nc (16 mb) a18 a17 a16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 mch ind/wait# nc wp# we# oe# ce# v cc nc v ss adv# ry/by# nc clk reset# v ccq a3 a4 a5 a6 a7 a8 v ss acc v cc a9 a10 a11 a12 a13 a14 a15 25 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80-pin pqfp
14 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary physical dimensions prq080?80-lead plastic quad flat package 3213\38.4 c package pqr 080 jedec mo-108(b)cb-1 notes symbol min nom max a -- -- 3.35 a1 0.25 -- -- a2 2.70 2.80 2.90 b 0.30 -- 0.45 see note 4 c 0.15 -- 0.23 d 17.00 17.20 17.40 d1 13.90 14.00 14.10 see note 3 d3 -- 12.0 -- reference e -- 0.80 -- basic, see note 7 e 23.00 23.20 23.40 e1 19.90 20.00 20.10 see note 3 e3 -- 18.40 -- reference aaa --- 0.20 --- ccc 0.10 l 0.73 0.88 1.03 p24 q40 r64 s80 notes: 1. all dimensions and tolerances conform to ansi y14.5m-1982. 2. datum plane -a- is located at the mold parting line and is coincident with the bottom of the lead where the lead exits the plastic body. 3. dimensions "d1" and "e1" do not includ mold protrusion. allowable protrusion is 0.25 mm per side. dimensions "d1" and "e1" include mold mismatch and are determined at datum plane -a- 4. dimension "b" does not include dambar protrusion. 5. controlling dimensions: millimeter. 6. dimensions "d" and "e" are measured from both innermost and outermost points. 7. deviation from lead-tip true position shall be within ?.0076 mm for pitch > 0.5 mm and within ?.04 for pitch < 0.5 mm. 8. lead coplanarity shall be within: (refer to 06-500) 1 - 0.10 mm for devices with lead pitch of 0.65 - 0.80 mm 2 - 0.076 mm for devices with lead pitch of 0.50 mm. coplanarity is measured per specification 06-500. 9. half span (center of package to lead tip) shall be within ?.0085". b c section s-s 6 3 3 6 -b- pin r pin s -a- pin one i.d. d1 d d3 pin q -d- pin p e e1 e3 see note 3 a a1 a2 -c- -a- seating plane 2 e basic see detail x s s detail x 0.25 a c ccc sd s 4 c ab m a a b 0?-7? a 0?min. l gage plane 7? typ. 0.30 ?0.05 r 7? typ. 0.20 min. flat shoulder
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 15 preliminary connection diagrams note: on 16 mb device, ball d3 (a19) is nc. special package handling instructions special handling is required for flash memory pr oducts in molded packages (bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 b7 c7 d7 e7 f7 g7 h7 b8 c8 d8 e8 f8 g8 h8 dq20 v ccq v ss v ccq dq29 a0 a1 dq18 dq23 dq24 dq26 dq30 mch a4 dq19 dq21 dq25 dq28 dq31 a7 a5 dq17 dq22 ry/by# dq27 nc nc a8 wp# dq9 dq5 dq1 nc a10 a9 dq11 dq10 dq6 dq2 a19 (32 mb)/ nc (16 mb) a11 a12 a3 a4 a5 a6 a7 a8 a2 a3 a6 v ss acc v cc b2 c2 d2 e2 f2 g2 h2 dq12 dq8 dq7 dq4 dq0 a18 a13 a2 a14 b1 c1 d1 e1 f1 g1 h1 dq13 j3 j4 j5 j6 j7 j8 dq16 ind/wait# oe# ce# nc adv# j2 dq14 j1 dq15 k3 k4 k5 k6 k7 k8 mch nc we# v cc v ss clk k2 reset# k1 v ccq v ccq v ss v ccq dq3 a17 a16 a1 a15 80-ball fortified bga
16 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary physical dimensions laa080?80-ball fortified ball grid array (13 x 11 mm) 3214\38.12c package laa 080 jedec n/a 13.00 x 11.00 mm note package symbol min nom max a -- -- 1.40 profile height a1 0.40 -- -- standoff a2 0.60 -- -- body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 9.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 10 matrix size d direction me 8 matrix size e direction n 80 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd/se 0.50 bsc solder ball placement notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row , sd or se = e/2 8. n/a 9. "+" indicates the theoretical center of depopulated balls. bottom view side view top view 2x 2x c 0.20 c 0.20 6 7 7 a c c 0.10 0.25 m m b c 0.25 0.15 c a b c seating plane j k ed (ink or laser) corner a1 a2 d e 0.50 a1 corner id. 1.00?.5 1.00?.5 a a1 corner a1 nx b sd se ee e1 d1 1 2 3 4 5 6 7 8 a cb d fe g h
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 17 preliminary pin configuration a0?a19 = 20-bit address bus for 32 mb device, (19-bit for 16 mb). a9 supports 12 v autoselect inputs. dq0?dq31 = 32-bit data inputs/outputs/float ce# = chip enable input. this signal is asynchronous relative to clk for the burst mode. oe# = output enable input. this signal is asynchronous relative to clk for the burst mode. we# = write enable. this signal is asynchronous relative to clk for the burst mode. v ss = device ground nc = pin not connected internally ry/by# = ready/busy output and open drain. when ry/by# = v oh , the device is ready to accept read operations and commands. when ry/by# = v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset operation. clk = clock input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. adv# = load burst address input. indicates that the valid address is present on the address inputs. ind# = end of burst indicator for finite bursts only. ind is low when the last word in the burst sequence is at the data outputs. wait# = provides data valid feedback only when the burst length is set to continuous. wp# = write protect input. when wp# = v ol , the two outermost bootblock sector in the 75% bank are write protected regardless of other sector protection configurations. acc = acceleration input. when taken to 12 v, program and erase operations are accelerated. when not used for acceleration, acc = v ss to v cc . v io (v ccq ) = output buffer power su pply (1.65 v to 2.75 v) v cc = chip power supply (2.5 v to 2.75 v) or (3.00 v to 3.60 v) reset# = hardware reset input mch = must connect high (to v cc )
18 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary logic symbols s29cd032g s29cd016g 20 32 dq0?dq31 a0?a19 clk ry/by# ce# oe# we# reset# adv# acc wp# v io (v ccq ) ind/wait# 19 32 dq0?dq31 a0?a18 clk ry/by# ce# oe# we# reset# adv# acc wp# v io (v ccq ) ind/wait#
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 19 preliminary memory map and sector protect groups the following tables lists the address ranges for all sectors and sector groups, and the sector sizes. notes: 1. secured silicon sector overlays this sector when enabled. 2. the bank address is determined by a19 and a18. ba = 00 for bank 0 and ba = 01, 10, or 11 for bank 1. 3. this sector has the additional wp# pin sector protection feature. 4. sector groups are for sector protection. ta b l e 2 3 . 32 mb memory map and sector protect groups for ordering option 00, top boot sector sector group note 4 x32 address range (a19:a0) sector size (kdwords) sector sector group note 4 x32 address range (a19:a0) sector size (kdwords) bank 0, small bank note 2 bank 1, large bank note 2 sa0 note 1 sg0 00000h?007ffh 2 sa23 sg12 40000h?43fffh 16 sa1 sg1 00800h?00fffh 2 sa24 44000h?47fffh 16 sa2 sg2 01000h?017ffh 2 sa25 48000h?4bfffh 16 sa3 sg3 01800h?01fffh 2 sa26 4c000h?4ffffh 16 sa4 sg4 02000h?027ffh 2 sa27 sg13 50000h?53fffh 16 sa5 sg5 02800h?02fffh 2 sa28 54000h?57fffh 16 sa6 sg6 03000h?037ffh 2 sa29 58000h?5bfffh 16 sa7 sg7 03800h?03fffh 2 sa30 5c000h?5ffffh 16 sa8 sg8 04000h?07fffh 16 sa31 sg14 60000h?63fffh 16 sa9 08000h?0bfffh 16 sa32 64000h?67fffh 16 sa10 0c000h?0ffffh 16 sa33 68000h?6bfffh 16 sa11 sg9 10000h?13fffh 16 sa34 6c000h?6ffffh 16 sa12 14000h?17fffh 16 sa35 sg15 70000h?73fffh 16 sa13 18000h?1bfffh 16 sa36 74000h?77fffh 16 sa14 1c000h?1ffffh 16 sa37 78000h?7bfffh 16 sa15 sg10 20000h?23fffh 16 sa38 7c000h?7ffffh 16 sa16 24000h?27fffh 16 sa39 sg16 80000h?83fffh 16 sa17 28000h?2bfffh 16 sa40 84000h?87fffh 16 sa18 2c000h?2ffffh 16 sa41 88000h?8bfffh 16 sa19 sg11 30000h?33fffh 16 sa42 8c000h?8ffffh 16 sa20 34000h?37fffh 16 sa43 sg17 90000h?93fffh 16 sa21 38000h?3bfffh 16 sa44 94000h?97fffh 16 sa22 3c000h?3ffffh 16 sa45 98000h?9bfffh 16 sa46 9c000h?9ffffh 16 sa47 sg18 a0000h?a3fffh 16 sa48 a4000h?a7fffh 16 sa49 a8000h?abfffh 16 sa50 ac000h?affffh 16 sa51 sg19 b0000h?b3fffh 16 sa52 b4000h?b7fffh 16 sa53 b8000h?bbfffh 16 sa54 bc000h?bffffh 16 sa55 sg20 c0000h?c3fffh 16 sa56 c4000h?c7fffh 16 sa57 c8000h?cbfffh 16 sa58 cc000h?cffffh 16 sa59 sg21 d0000h?d3fffh 16 sa60 d4000h?d7fffh 16 sa61 d8000h?dbfffh 16 sa62 dc000h?dffffh 16 sa63 sg22 e0000h?e3fffh 16 sa64 e4000h?e7fffh 16 sa65 e8000h?ebfffh 16 sa66 ec000h?effffh 16 sa67 sg23 f0000h?f3fffh 16 sa68 f4000h?f7fffh 16 sa69 f8000h?fbfffh 16 sa70 sg24 fc000h?fc7ffh 2 sa71 sg25 fc800h?fcfffh 2 sa72 sg26 fd000h?fd7ffh 2 sa73 sg27 fd800h?fdfffh 2 sa74 sg28 fe000h?fe7ffh 2 sa75 sg29 fe800h?fefffh 2 sa76 note 3 sg30 ff000h?ff7ffh 2 sa77 note 3 sg31 ff800h?fffffh 2
20 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary notes: 1. this sector has the additional wp # pin sector protection feature. 2. the bank address is determined by a19 and a18. ba = 00, 01, or 10 for bank 0 and ba = 11 for bank 1. 3. secured silicon sector overla ys this sector when enabled. 4. sector groups are for sector protection. ta b l e 2 4 . 32 mb memory map and sector protect groups for ordering option 01, bottom boot sector sector group note 4 x32 address range (a19:a0) sector size (kdwords) sector sector group note 4 x32 address range (a19:a0) sector size (kdwords) bank 0, large bank note 2 bank 1, small bank (note 2) sa0 note 1 sg0 00000h?007ffh 2 sa55 sg20 c0000h?c3fffh 16 sa1 note 1 sg1 00800h?00fffh 2 sa56 c4000h?c7fffh 16 sa2 sg2 01000h?017ffh 2 sa57 c8000h?cbfffh 16 sa3 sg3 01800h?01fffh 2 sa58 cc000h?cffffh 16 sa4 sg4 02000h?027ffh 2 sa59 sg21 d0000h?d3fffh 16 sa5 sg5 02800h?02fffh 2 sa60 d4000h?d7fffh 16 sa6 sg6 03000h?037ffh 2 sa61 d8000h?dbfffh 16 sa7 sg7 03800h?03fffh 2 sa62 dc000h?dffffh 16 sa8 sg8 04000h?07fffh 16 sa63 sg22 e0000h?e3fffh 16 sa9 08000h?0bfffh 16 sa64 e4000h?e7fffh 16 sa10 0c000h?0ffffh 16 sa65 e8000h?ebfffh 16 sa11 sg9 10000h?13fffh 16 sa66 ec000h?effffh 16 sa12 14000h?17fffh 16 sa67 sg23 f0000h?f3fffh 16 sa13 18000h?1bfffh 16 sa68 f4000h?f7fffh 16 sa14 1c000h?1ffffh 16 sa69 f8000h?fbfffh 16 sa15 sg10 20000h?23fffh 16 sa70 sg24 fc000h?fc7ffh 2 sa16 24000h?27fffh 16 sa71 sg25 fc800h?fcfffh 2 sa17 28000h?2bfffh 16 sa72 sg26 fd000h?fd7ffh 2 sa18 2c000h?2ffffh 16 sa73 sg27 fd800h?fdfffh 2 sa19 sg11 30000h?33fffh 16 sa74 sg28 fe000h?fe7ffh 2 sa20 34000h?37fffh 16 sa75 sg29 fe800h?fefffh 2 sa21 38000h?3bfffh 16 sa76 sg30 ff000h?ff7ffh 2 sa22 3c000h?3ffffh 16 sa77 note 3 sg31 ff800h?fffffh 2 sa23 sg12 40000h?43fffh 16 sa24 44000h?47fffh 16 sa25 48000h?4bfffh 16 sa26 4c000h?4ffffh 16 sa27 sg13 50000h?53fffh 16 sa28 54000h?57fffh 16 sa29 58000h?5bfffh 16 sa30 5c000h?5ffffh 16 sa31 sg14 60000h?63fffh 16 sa32 64000h?67fffh 16 sa33 68000h?6bfffh 16 sa35 sg15 70000h?73fffh 16 sa36 74000h?77fffh 16 sa37 78000h?7bfffh 16 sa38 7c000h?7ffffh 16 sa39 sg16 80000h?83fffh 16 sa40 84000h?87fffh 16 sa41 88000h?8bfffh 16 sa42 8c000h?8ffffh 16 sa43 sg17 90000h?93fffh 16 sa44 94000h?97fffh 16 sa45 98000h?9bfffh 16 sa46 9c000h?9ffffh 16 sa47 sg18 a0000h?a3fffh 16 sa48 a4000h?a7fffh 16 sa49 a8000h?abfffh 16 sa50 ac000h?affffh 16 sa51 sg19 b0000h?b3fffh 16 sa52 b4000h?b7fffh 16 sa53 b8000h?bbfffh 16 sa54 bc000h?bffffh 16
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 21 preliminary notes: 1. secured silicon sector overlays this sector when enabled. 2. the bank address is determined by a18 and a17. ba = 00 for bank 1 and ba = 01, 10, or 11 for bank 2. 3. this sector has the additional wp# pin sector protection feature. 4. sector groups are for sector protection. table 25. 16 mb, memory map and sector protect groups for ordering option 00, top boot sector sector group x32 address range (a18:a0) sector size (kdwords) sector sector group x32 address range (a18:a0) sector size (kdwords) bank 0 , small bank note 2 bank 1, large bank note 2 sa0 note 1 sg0 00000h?007ffh 2 sa15 sg10 20000h?23fffh 16 sa1 sg1 00800h?00fffh 2 sa16 24000h?27fffh 16 sa2 sg2 01000h?017ffh 2 sa17 28000h?2bfffh 16 sa3 sg3 01800h?01fffh 2 sa18 2c000h?2ffffh 16 sa4 sg4 02000h?027ffh 2 sa19 sg11 30000h?33fffh 16 sa5 sg5 02800h?02fffh 2 sa20 34000h?37fffh 16 sa6 sg6 03000h?037ffh 2 sa21 38000h?3bfffh 16 sa7 sg7 03800h?03fffh 2 sa22 3c000h?3ffffh 16 sa8 sg8 04000h?07fffh 16 sa23 sg12 40000h?43fffh 16 sa9 08000h?0bfffh 16 sa24 44000h?47fffh 16 sa10 0c000h?0ffffh 16 sa25 48000h?4bfffh 16 sa11 sg9 10000h?13fffh 16 sa26 4c000h?4ffffh 16 sa12 14000h?17fffh 16 sa27 sg13 50000h?53fffh 16 sa13 18000h?1bfffh 16 sa28 54000h?57fffh 16 sa14 1c000h?1ffffh 16 sa29 58000h?5bfffh 16 sa30 5c000h?5ffffh 16 sa31 sg14 60000h?63fffh 16 sa32 64000h?67fffh 16 sa33 68000h?6bfffh 16 sa34 6c000h?6ffffh 16 sa35 sg15 70000h?73fffh 16 sa36 74000h?77fffh 16 sa37 78000h?7bfffh 16 sa38 sg16 7c000h?7c7ffh 2 sa39 sg17 7c800h?7cfffh 2 sa40 sg18 7d000h?7d7ffh 2 sa41 sg19 7d800h?7dfffh 2 sa42 sg20 7e000h?7e7ffh 2 sa43 sg21 7e800h?7efffh 2 sa44 note 2 sg22 7f000h?7f7ffh 2 sa45 note 2 sg23 7f800h?7ffffh 2
22 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary notes: 1. this sector has the additional wp# pin sector protection feature. 2. the bank address is determined by a18 and a17. ba = 00 for bank 1 and ba = 01, 10, or 11 for bank 2. 3. secured silicon sector overla ys this sector when enabled. 4. sector groups are for sector protection. table 26. 16 mb, memory map and sector protec t groups for ordering option 00, bottom boot sector sector group note 4 x32 address range (a19:a0) sector size (kdwords) sector sector group note 4 x32 address range (a19:a0) sector size (kdwords) bank 0, large bank note 2 bank 1, small bank note 2 sa0 note 1 sg0 00000h?007ffh 2 sa35 sg15 70000h?73fffh 16 sa1 note 1 sg1 00800h?00fffh 2 sa36 74000h?77fffh 16 sa2 sg2 01000h?017ffh 2 sa37 78000h?7bfffh 16 sa3 sg3 01800h?01fffh 2 sa38 sg16 7c000h?7c7ffh 2 sa4 sg4 02000h?027ffh 2 sa39 sg17 7c800h?7cfffh 2 sa5 sg5 02800h?02fffh 2 sa40 sg18 7d000h?7d7ffh 2 sa6 sg6 03000h?037ffh 2 sa41 sg19 7d800h?7dfffh 2 sa7 sg7 03800h?03fffh 2 sa42 sg20 7e000h?7e7ffh 2 sa8 sg8 04000h?07fffh 16 sa43 sg21 7e800h?7efffh 2 sa9 08000h?0bfffh 16 sa44 sg22 7f000h?7f7ffh 2 sa10 0c000h?0ffffh 16 sa45 sg23 7f800h?7ffffh 2 sa11 sg9 10000h?13fffh 16 sa12 14000h?17fffh 16 sa13 18000h?1bfffh 16 sa14 1c000h?1ffffh 16 sa15 sg10 20000h?23fffh 16 sa16 24000h?27fffh 16 sa17 28000h?2bfffh 16 sa18 2c000h?2ffffh 16 sa19 sg11 30000h?33fffh 16 sa20 34000h?37fffh 16 sa21 38000h?3bfffh 16 sa22 3c000h?3ffffh 16 sa23 sg12 40000h?43fffh 16 sa24 44000h?47fffh 16 sa25 48000h?4bfffh 16 sa26 4c000h?4ffffh 16 sa27 sg13 50000h?53fffh 16 sa28 54000h?57fffh 16 sa29 58000h?5bfffh 16 sa30 5c000h?5ffffh 16 sa31 sg14 60000h?63fffh 16 sa32 64000h?67fffh 16 sa33 68000h?6bfffh 16 sa34 6c000h?6ffffh 16
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 23 preliminary device operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addres- sable memory location. the register is composed of latches that store the commands, along with the address and data information needed to exec ute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 2 7 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. legend: l = logic low = v il , h = logic high = v ih , x = don?t care. notes: 1. wp# controls the two outermost sectors of the top boot bl ock or the two outermost sectors of the bottom boot block. 2. dq0 reflects the sector ppb (or sect or group ppb) and dq1 reflects the dyb versatilei/o? (v io ) control the versatilei/o (v io ) control allows the host system to set the voltage levels that the device gen- erates at its data outputs and the voltages tolera ted at its data inputs to the same voltage level that is asserted on the v io pin. the output voltage generated on the device is determined based on the v io (v ccq ) level. for the 2.6 v v cc mask option, a v io of 1.65 v ? 1.95 v allows the device to interface with i/os lower than 2.5 v. vcc = vio (2.5 v to 2.75v) make the device appear as a 2.5 v only. requirements for reading array data to read array data from the outputs, the sy stem must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . ta b l e 2 7 . device bus operation operation ce# oe# we# reset# clk adv# addresses data (dq0?dq31) read l l h h x x a in d out asynchronous write l h l h x x a in d in synchronous write l h l h a in d in standby (ce#) h x x h x x x high z output disable l h h h x x high z high z reset x x x l x x x high z ppb protection status (note 2) l l h h x x sector address, a9 = v id , a7 ? a0 = 02h 00000001h, (protected) a6 = h 00000000h (unprotect) a6 = l burst read operations load starting burst address l x h h a in x advance burst to next address with appropriate data presented on the data bus l l h h h x burst data out terminate current burst read cycle h x h h x x high z terminate current burst read cycle with reset# x x h l x x x high z terminate current burst read cycle; start new burst read cycle l h h h a in x
24 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register con- tents are altered. address access time (t acc ) is the delay from stable addresses to valid output data. the chip en- able access time (t ce ) is the delay from stable addresses and stable ce# to valid data at the output pins. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output pins (assuming the addresses were stable for at least t acc ?t oe time and ce# is asserted for at least t ce ?t oe time). see reading array data in non-burst mode and reading array data in burst mode for more infor- mation. refer to the asynchronous read operations table for timing specifications and to figure 15 for the timing diagram. i cc1 in the dc characteristics table represents the active cur- rent specification for reading array data. simultaneous read/write operations overview overview the simultaneous read/write feature allows embedded program or embedded erase operation to be executed in the small bank, while reading from the large bank. the opposite case is not valid. note: please refer to the memory map table 23 , table 24 , table 25 , and table 26 for small and large bank assignments. program/erase suspend and simultaneous operation there is no restriction to implementing a prog ram-suspend or erase-suspend during a simulta- neous operation. common flash interface (cfi) an d password program/verify and simultaneous operation simultaneous read/write operation is disabled during the cfi and password program/verify oper- ation, including ppb program/erase and unlocking a password operation. only array data can be read in the large bank during a simultaneous operation. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. see sector erase and program suspend command on page 47 for details on pro- gramming data to the device using both st andard and unlock bypass command sequences. table 28. allowable conditions for simultaneous operation small bank large bank embedded erase burst (synchronous) read or asynchronous read embedded program burst (synchronous) read or asynchronous read
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 25 preliminary an erase operation can erase one sector, mu ltiple sectors, or the entire device. ta b l e 2 3 , ta b l e 2 4 , ta b l e 2 5 , and table 26 indicate the address space that each sector occupies. a sector address consists of the address bits required to uniquely select a sector. see command definitions on page 42 for details on erasing a sector or the en tire chip, or suspending/resuming the erase operation. when in synchronous read mode configuration, the device is able to perform both asynchronous and synchronous write operations. clk and adv# address latch is supported in synchronous pro- gramming mode. during a synchronous write operation, to write a command or command sequence, (which includes programming data to the device and erasing sectors of memory), the system must drive adv# and ce# to vil, and oe # to vih when providing an address to the de- vice, and drive we# and ce# to vil, and ce # to vih, when writing commands or data. accelerated program and erase operations the device offers accelerated program/erase oper ations through the acc pin. when the system asserts v hh (12v) on the acc pin, the device automati cally enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence to do acceler- ated programming. the device uses the higher voltage on the acc pin to accelerate the operation. a sector that is being protected with the wp# pin is protected during accelerated program or erase. note: the acc pin must not be at v hh during any operation other than accelera ted programming, or device damage can result. autoselect functions if the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. see autoselect mode on page 26 and autoselect command on page 43 for more information. automatic sleep mode (asm) the automatic sleep mode minimizes flash device energy consumption. while in asynchronous mode, the device automatically enables this mode when addresses remain stable for t acc + 60 ns. the automatic sleep mode is independent of the ce#, we# and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, out- put data is latched and always available to the system. while in synchronous mode, the device automatically enables this mode when either the first active clk level is greater than t acc or the clk runs slower than 5 mhz. note that a new bu rst operation is required to provide new data. i cc8 in dc characteristics on page 64 represents the automatic sleep mode current specification. standby mode when the system is not responding or writing to the device, it can place the device in the standby mode. in this mode, current consumption is grea tly reduced, and the outputs are placed in the high impedance state, inde pendent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at vcc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc5 in dc characteristics on page 64 represents the standby current specification. caution : entering the standby mode via the reset# pin also resets the device to the read mode and floats the data i/o pins. furthermore, entering i cc7 during a program or erase operation
26 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary leaves erroneous data in the address locations bein g operated on at the time of the reset# pulse. these locations require updating after the device resumes standard operations. see reset#: hardware reset pin on page 26 for further discussion of the reset# pin and its functions. reset#: hardware reset pin the reset# pin is an active low signal that is used to reset the device under any circumstances. a logic 0 on this pin forces the device out of any mode that is currently executing back to the reset state. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device. to avoid a potential bus contention during a system reset, the device is isolated from the dq data bus by tristating the data output pins for the duration of the reset pulse. all pins are don?t cares during the reset operation. if reset# is asserted during a program or erase operation, the ry/by# pin remains low until the reset operation is internally complete. this action requires between 1 s and 7s for either chip erase or sector erase. the ry/by# pin can be used to determine when the reset operation is com- plete. otherwise, allow for the maximum reset ti me of 11 s. if reset# is asserted when a program or erase operation is not executing (ry/by# = 1 ), the reset operation completes within 500 ns. the simultaneous read/write feature of this device allows the user to read a bank after 500 ns if the bank was in the read/reset mode at the time reset# was asserted. if one of the banks was in the middle of either a program or erase operation when reset# was asserted, the user must wait 11 s before accessing that bank. asserting reset# during a progra m or erase operation leaves erroneous data stored in the ad- dress locations being operated on at the time of device reset. these locations need updating after the reset operation is complete. see figure 19, reset# timings, on page 72 for timing specifications. asserting reset# active during v cc and v io power up is required to guarantee proper device ini- tialization until v cc and v io reaches steady state voltages. output disable mode see table 27 on page 23 device bus operation for oe# operation in output disable mode. autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection ver- ification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its correspond- ing programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. ad- dress pins a6, a1, and a0 must be as shown in table 24 on page 20 (top boot devices) or ta b l e 2 5 on page 21 (bottom boot devices). in addition, when verifying sector protection, the sector ad- dress must appear on the appropriate highest order address bits (see table 23 on page 19 through table 26 on page 22 ). table 29 shows the remaining address bits that are don?t care. when all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command. this method does not require v id . see command definitions on page 42 for details on using the autoselect mode.
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 27 preliminary legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: the autoselect codes can also be accessed in-system via command sequences. see table 40 on page 48 and table 42 on page 55 . asynchronous read operation (non-burst) the device has two control functions which must be satisfied in order to obtain data at the out- puts. ce# is the power control and is used for device selection. oe# is the output control and is used to gate data to the output pins if the device is selected. the device is powered-up in an asyn- chronous read mode. in the asynchronous mode the device has two control functions which must be satisfied in order to obtain data at the outputs. ce# is the power control and is used for device selection. oe# is the output control and is used to gate data to the output pins if the device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and stable ce# to valid data at the output pins. the output enable access time is the delay from the falling edge of oe# to valid data at the output pins (assuming the addresses are stable for at least t acc ?t oe time). note: operation is shown for the 32-bit data bus. for the 16-bit data bus, a-1 is required. figure 1. asynchronous read operation synchronous (burst) read operation the device is capable of performing burst read operations to improve total system data through- put. the 2, 4, and 8 double word accesses are configurable as linear burst accesses. all burst ta b l e 2 9 . s29cd-g flash family autoselect codes (high voltage method) description ce# oe# we# a19 to a11 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq7 to dq0 manufacturer id : spansion l l h x x v id x x l x x x l l 0001h autoselect device code read cycle 1 l l h x x v id x l l x l l l h 007eh read cycle 2 l l h x x v id x l l l h h h l 0036h (16mb) 0009h (32mb) read cycle 3 l l h x x v id x l l l h h h h 0000h ordering option 00 0001h ordering option 01 ppb protection status l l h sa x v id x l l l l l h l 0000h (unprotected) 0001h (protected) d0 d1 d2 d3 d3 ce# clk adv# addresses data oe# we# ind/wait# v ih float v oh address 0 address 1 address 2 address 3 float
28 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary operations provide wrap around linear burst acce sses. additional options for all burst modes in- clude initial access delay conf igurations (2?16 clks) device configuration fo r burst mode operation is accomplished by writing the configuration register with the desired burst configura- tion information. once the configuration register is written to enable burst mode operation, all subsequent reads from the array are returned us ing the burst mode protocols. like the main memory access, the secured silicon sector memory is accessed with the same burst or asynchro- nous timing as defined in the configuration register. however, the user must recognize burst operations past the 256 byte secured silicon boundary returns invalid data. burst read operations occur only to the main fl ash memory arrays. the configuration register and protection bits are treated as single cycle reads, even when burst mode is enabled. read opera- tions to these locations results in the data remaining valid while oe# is at v il , regardless of the number of clk cycles applied to the device. linear burst read operations linear burst read mode reads either 2, 4, or 8 double words (1 double word = 32 bits). (see table 30 for all valid burst output sequences). the ind/wait# pin transitions active (v il ) during the last transfer of data during a linear burst re ad before a wrap around, indicating that the sys- tem should initiate another adv# to start the next burst access. if the system continues to clock the device, the next access wraps around to the starting address of the previous burst access. the ind/wait# signal remains inactive (floating) when not active. see ta b l e 3 0 for a complete 32 data bus interface order. ce# control in linear mode the ce# (chip enable) pin enables the device duri ng read mode operations. ce# must meet the required burst read setup times for burst cycle initiation. if ce# is taken to v ih at any time during the burst linear or burst cycle, the device immediately exits the burst sequence and floats the dq bus signal. restarting a burst cycle is accomplished by taking ce# and adv# to v il . adv# control in linear mode the adv# (address valid) pin is used to initiate a linear burst cycle at the clock edge when ce# and adv# are at v il and the device is configured for either linear burst mode operation. a burst access is initiated and the address is latched on th e first rising clk edge when adv# is active or upon a rising adv# edge, whichever occurs first. if the adv# signal is taken to v il prior to the end of a linear burst sequence, the previous a ddress is discarded and subs equent burst transfers are invalid until adv# transitions to v ih before a clock edge, which initiates a new burst sequence. ta b l e 3 0 . 32- bit linear and burst data order data transfer sequence (independent of the word# pin) output data sequence (initial access address) two linear data transfers 0-1 (a0 = 0) 1-0 (a0 = 1) four linear data transfers 0-1-2-3 (a0:a-1/a1-a0 = 00) 1-2-3-0 (a0:a-1/a1-a0 = 01) 2-3-0-1 (a:a-1/a1-a0 = 10) 3-0-1-2 (a0:a-1/a1-a0 = 11) eight linear data transfers 0-1-2-3-4-5-6-7 (a1:a-1a2-a0 = 000) 1-2-3-4-5-6-7-0 (a1:a-1/a2-a0 = 001) 2-3-4-5-6-7-0-1 (a1:a-1/a2-a0 = 010) 3-4-5-6-7-0-1-2 (a1:a-1/a2-a0 = 011) 4-5-6-7-0-1-2-3 (a1:a-1/a2-a0 = 100) 5-6-7-0-1-2-3-4 (a1:a-1/a2-a0 = 101) 6-7-0-1-2-3-4-5 (a1:a-1/a2-a0 = 110) 7-0-1-2-3-4-5-6 (a1:a-1/a2-a0 = 111)
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 29 preliminary reset# control in linear mode the reset# pin immediately halts the linear burst access when taken to v il . the dq data bus signal float. additionally, the configuration regist er contents are reset back to the default condi- tion where the device is placed in asynchronous access mode. oe# control in linear mode the oe# (output enable) pin is used to enable the linear burst data on the dq data bus pin. de- asserting the oe# pin to v ih during a burst operation floats the data bus. however, the device continues to operate internally as if the burst sequence continues until the linear burst is com- plete. the oe# pin does not halt the burst sequence, this is accomplished by either taking ce# to v ih or re-issuing a new adv# pulse. the dq bus remains in the float state until oe# is taken to v il . ind/wait# operation in linear mode the ind/wait#, or end of burst indicator signal (when in linear modes), informs the system that the last address of a burst sequence is on the dq data bus. for example, if a 2-double-word linear burst access is enabled using a 16-bit dq bus (word# = v il ), the ind/wait# signal transitions active on the second access. if the same scen ario is used, the ind/wait# signal has the same delay and setup timing as the dq pins. also, the ind/wait# signal is controlled by the oe# sig- nal. if oe# is at v ih , the ind/wait# signal floats and is not driven. if oe# is at v il , the ind/ wait# signal is driven at v ih until it transitions to v il indicating the end of burst sequence. the ind/wait# signal timing and duration is (see configuration register on page 31 for more infor- mation). the following table lists the valid combin ations of the configuration register bits that impact the ind/wait# timing. note: operation is shown for the 32-bit data bus. figure shown wi th 3-clk initial access delay configuration, linear address, 4-doubleword burst, output on rising cld edge, data hold for 1-clk, ind/wait# asserted on the last transfer before wrap- around. figure 2. end of burst indicator (ind/wait#) timi ng for linear 8-word burst operation ta b l e 3 1 . valid configuration register bit definition for ind/wait# doc wc cc definition 0 0 1 ind/wait# = vil for 1-clk cycle, active on last transfer, driven on rising cld edge 0 1 1 ind/wait# = vil for 1-clk cycle, active on second to last transfer, driven on rising clk edge ce# clk adv# addresses oe# data address 1 address 2 invalid d1 d2 d3 d0 address 1 latched 3 clock delay ind/wait# v il v ih
30 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary burst access timing control in addition to the ind/wait# signal control, burst controls exist in the control register for initial access delay, delivery of data on the clk edge, and the length of time data is held. initial burst access delay control the device contains options for initial access delay of a burst access. the initial access delay has no effect on asynchro nous read operations. burst initial access delay is defined as the number of clock cycles that must elapse from the first valid clock edge after adv# assertion (or the rising edge of adv#) until the first valid clk edge when the data is valid. the burst access is initiated and the address is latched on the first rising clk edge when adv# is active or upon a rising adv# edge, whichever comes first. ( ta b l e 3 2 describes the initial access delay configurations.) notes: 1. burst access starts with a rising clk edge and when adv# is active. 2. configurations register 6 is always set to 1 (cr6 = 1). burst starts and data outputs on the rising clk edge. 3. cr [13-10] = 1 or three clock cycles 4. cr [13-10] = 2 or four clock cycles 5. cr [13-10] = 3 or five clock cycles figure 3. initial burst delay control burst clk edge data delivery the device delivers data on the rising of clk. bit 6 in the control register (cr6) is set to 1, and is the default configuration. burst data hold control the device is capable of holding data for one clks. the default configuration is to hold data for one clk and is the only valid state. ta b l e 3 2 . burst initial access delay cr13 cr12 cr11 cr10 initial burst access (clk cycles) 40 mhz (0j), 56 mhz (0m), 66 mhz (0p), 75 mhz (0r, 32 mb only) 0 0 0 0 2 0 0 0 1 3 0 0 1 0 4 0 0 1 1 5 0 1 0 0 6 0 1 0 1 7 0 1 1 0 8 0 1 1 1 9 clk adv# addresses dq31-dq0 3 dq31-dq0 4 dq31-dq0 5 valid address three clk delay 2nd clk 3rd clk 4th clk 5th clk 1st clk four clk delay address 1 latched five clk delay d0 d1 d2 d3 d0 d1 d2 d0 d1 d2 d3 d4
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 31 preliminary asserting reset# during a burst access if reset# is asserted low during a burst access, the burst access is immediately terminated and the device defaults back to asynchronous read mode. see hardware reset (reset#) on page 71 for more information on the reset# function. configuration register the device contains a configuration register fo r configuring read accesses. the configuration register is accessed by the configuration register read and the configuration register write com- mands. the configuration register does not occu py any addressable memory location, but rather, is accessed by the configuration register command s. the configuration register is readable any time, however, writing the configuration register is restricted to times when the embedded algo- rithm? is not active. if the user attempts to wr ite the configuration register while the embedded algorithm? is active, the write operation is ignore d and the contents of the configuration register remain unchanged. the configuration register is a 16 bit data field which is accessed by dq15?dq0. during a read operation, dq31?dq16 returns all zeroes. table 33 shows the configuration register. also, con- figuration register reads operate the same as autoselect command reads. when the command is issued, the bank address is latched along with the command. reads operations to the bank that was specified during the configuration register read command return configuration register con- tents. read operations to the other bank retu rn flash memory data. either bank address is permitted when writing the configuration register read command.
32 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary ta b l e 3 3 . configuration register definitions cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 rm asd iad3 iad2 iad1 iad0 doc wc cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 bs cc reserved reserved reserved bl2 bl1 bl0 configuration register cr15 = read mode (rm) 0 = synchronous burst reads enabled 1 = asynchronous reads enabled (default) cr14 = reserved for future enhancements 0 = asm enable 1 = asm disable cr13?cr10 = automatic sleep mode disable speed options 40, 56, and 66 mhz: 0000 = 2 clk cycle initial burst access delay 0001 = 3 clk cycle initial burst access delay 0010 = 4 clk cycle initial burst access delay 0011 = 5 clk cycle initial burst access delay 0100 = 6 clk cycle initial burst access delay 0101 = 7 clk cycle initial burst access delay 0110 = 8 clk cycle initial burst access delay 0111 = 9 clk cycle initial burst access delay?default cr9 = data output configuration (doc) 0 = hold data for 1-clk cycle?default 1 = reserved cr8 = ind/wait# configuration (wc) 0 = ind/wait# asserted during delay?default 1 = ind/wait# asserted one data cycle before delay cr7 = burst sequence (bs) 0 = reserved 1 = linear burst order?default cr6 = clock configuration (cc) 0 = reserved 1 = burst starts and data output on rising clock edge?default cr5?cr3 = reserved for future enhancements (r) these bits are reserved for fu ture use. set these bits to 0 . cr2?cr0 = burst length (bl2?bl0) 000 = reserved, burst accesses disabled (asynchronous reads only) 001 = 64 bit (8-byte) burst data transfer - x32 linear 010 = 128 bit (16-byte) burst data transfer - x32 linear 011 = 256 bit (32-byte) burst data transfer - x32 linear (device default) 100 = reserved, burst accesses disabled (asynchronous reads only) 101 = reserved, burst accesses disabled (asynchronous reads only) 110 = reserved, burst accesses disabled (asynchronous reads only)
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 33 preliminary initial access delay configuration the frequency configuration informs the device of the number of clocks that must elapse after adv# is driven active before data is available. this value is determined by the input clock frequency. sector protection the device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups sector and sector groups the distinction between sectors and sector groups is fundamental to sector protection. sector are individual sectors that can be individually sect or protected/unprotected. these are the outermost 4 kword boot sectors, that is, sa0 to sa7 and sa70 to sa77. see table 35 on page 35 , ta b l e 2 3 on page 19 , table 24 on page 20 , table 25 on page 21 , and table 26 on page 22 . sector groups are a collection of three or four adjacent 32 kword sectors. for example, sector group sg8 is comprised of sector sa8 to sa10. when any sector in a sector group is protected/ unprotected, every sector in that group is protection/unprotected. see table 35 , table 23 , table 24 , ta b l e 2 5 , and ta b l e 2 6 . persistent sector protection a command sector protection method that replac es the old 12 v controlled protection method. password sector protection a highly sophisticated protection method that requires a password before changes to certain sec- tors or sector groups are permitted. wp# hardware protection a write protect pin that can prevent program or erase to the two outermost 8 kbytes sectors in the 75% bank. all parts default to operate in the persistent sector protection mode. the customer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method is used. if the cus- tomer decides to continue using the persistent sector protection method, they must set the persistent sector protec tion mode locking bit . this permanently sets the part to operate only using persistent sector protection. if the customer decides to use the password method, they must set the password mode locking bit . this permanently sets the part to operate only using password sector protection. it is important to remember that setting either the persistent sector pr otection mode lock- ing bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit is set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on ta b l e 3 4 . configuration register after device reset cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 rm reserve iad3 iad2 iad1 iad0 doc wc 1 0 0 1 1 1 0 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 bs cc reserve reserve reserve bl2 bl1 bl0 1 1 0 0 0 1 0 0
34 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary the default mode alone. this is so that it is not possible for a system program or virus to later set the password mode locking bit, which would cause an unexpected shift from the default per- sistent sector protection mode into the password protection mode. the wp# hardware protection feature is always av ailable, independent of the software managed protection method chosen. persistent sector protection the persistent sector protection method replaces the old 12 v controlled protection method while at the same time enhancing flex ibility by providing three differe nt sector protection states: ? persistently locked ?a sector is protected and cannot be changed. ? dynamically locked ?the sector is protected and can be changed by a simple command ? unlocked ?the sector is unprotected and ca n be changed by a simple command in order to achieve these states, three types of bits are going to be used: persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to a maximum of four sectors (see the sector address tables for specific sector protection groupings). all 8 kbyte boot-block sectors have individual sector persistent protection bits (ppbs) for greater flexibility. each ppb is individually modifiable through the ppb write command . note: if a ppb requires erasure, all of the sector ppb s must first be preprogrammed prior to ppb eras - ing. all ppbs erase in parallel, unlike programming wh ere individual ppbs are programmable. it is the responsibility of the user to perform the preprogra mming operation. otherwise, an already erased sec - tor ppbs has the potential of being over-erased. th ere is no hardware mechanism to prevent sector ppbs over-erasure. persistent protection bit lock (ppb lock) a global volatile bit. when set to 1 , the ppbs cannot be changed. when cleared ( 0 ), the ppbs are changeable. there is only one ppb lock bit per de vice. the ppb lock is cleared after power-up or hardware reset. there is no command sequence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each se ctor. after power-up or hardware reset, the con- tents of all dybs is 0 . each dyb is individually modifi able through the dyb write command. when the parts are first shipped, the ppbs are cleared, the dybs are cleared, and ppb lock is defaulted to power up in the cleared st ate ? meaning the ppbs are changeable. when the device is first powered on the dybs power up cleared (sectors not protected). the pro- tection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppbs cleared, the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write command sequences, the dybs is set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of pro- tection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and difficult to change, level of protection. the ppbs retain state across power cycles because they are non-volatile. individual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are limited to 100 erase cycles. the ppb lock bit adds an additional level of pr otection. once all ppbs are programmed to the de- sired settings, the ppb lock may be set to 1 . setting the ppb lock disables all program and erase
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 35 preliminary commands to the non-volatile ppbs. in effect, the ppb lock bit locks the ppbs into the current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the ppb are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code ca n set the ppb lock to disable any further changes to the ppbs during system operation. the wp# write protect pin adds a final level of hardware protection to the two outermost 8 kbytes sectors in the 75% bank. when this pin is low it is not possible to change the contents of these two sectors. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb write command sequence is all that is necessary. the dyb write com- mand for the dynamic sectors switch the dybs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabl ed by either putting the device through a power- cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again, locks the ppbs and the device operates normally again. note: to achieve the best protection, it?s recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . table 35 contains all possible combinations of the dy b, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is prot ected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynamically locked or unlocked. the dyb then controls whether or not the sector is pro- tected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for ap- proximately 1 s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approx- imately 50 s after which the device returns to read mode without having erased the protected sector. the programming of the dyb, ppb, and ppb lock fo r a given sector can be verified by writing a dyb/ppb/ppb lock verify command to the device. persistent sector protection mode locking bit like the password mode locking bit, a persistent sector protection mode locking bit exists to guar- antee that the device remain in software sect or protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. this guarantees that an unauthorized user could not place the device in password protection mode. ta b l e 3 5 . sector protection schemes dyb ppb ppb lock sector state 0 0 0 unprotected?ppb and dyb are changeable 0 0 1 unprotected?ppb not changeable, dyb is changeable 0 1 0 protected?ppb and dyb are changeable 1 0 0 1 1 0 0 1 1 protected?ppb not changeable, dyb is changeable 1 0 1 1 1 1
36 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary password protection mode the password sector protection mode method allows an even higher level of security than the per- sistent sector protection mode. there are two ma in differences between the persistent sector protection and the password sector protection mode: ? when the device is first powered on, or comes out of a reset cycle, the ppb lock bit set to the locked state , rather than cleared to the unlocked state. ? the only means to clear the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a one-time programmable (otp) region of the flash memory. once the password mode locking bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear the ppb lock bit. the password unlock com- mand must be written to the flash, along with a password. the flash device internally compares the given password with the pre-programmed passw ord. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each password check . this delay is intended to stop any efforts to run a program that tries all possible combinations in order to crack the password. password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the password. one method of choosing a password would be to correlate it to the unique electronic serial number (esn) of the particular flash device. another method could generate a database where all the passwords are stored, each of which correlates to a serial number on the device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: 1) it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. 2) it also disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode locking bit, there is no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once pass- word mode locking bit is programmed, the persistent sector protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify commands (see password verify command ). the password function
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 37 preliminary works in conjunction with the password mode lock ing bit, which when set, prevents the password verify command from reading the contents of the password on the pins of the device. write protect (wp#) the device features a hardware protection option using a write protect pin that prevents program- ming or erasing, regardless of the state of the se ctor?s persistent or dynamic protection bits. the wp# pin is associated with the two outermost 8kbytes sectors in the 75% bank. the wp# pin has no effect on any other sector. when wp# is taken to v il , programming and erase operations of the two outermost 8 kbytes sectors in the 75% bank are disabled. by taking wp# back to v ih , the two outermost 8 kbytes sectors are enabled for program and erase operations, depending upon the status of the individual sector persistent or dynamic protection bits. if either of the two outermost sectors persistent or dynamic protecti on bits are programmed, program or erase op- erations are inhibited. if the sector persistent or dynamic protection bits are both erased, the two sectors are available for programming or erasing as long as wp# remains at v ih . the user must hold the wp# pin at either v ih or v il during the entire program or erase operation of the two outermost sectors in the 75% bank. secured silicon otp sector and simultaneous operation the secured silicon sector is 256 kbytes and is located in the small bank. for s29cd016g and s29cd032g devices. spansion programs and permanently locks the secured silicon sector with unique device identification. please contact your sales representative for the electronic marking information. since the secured silicon is permanent protected by spansion, during simultaneous operation, the secured silicon sector cannot be erased or reprogrammed. persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode locking bit after power-up reset. if the password mode locking bit is set, which indicates the device is in password protection mode, the ppb lock bit is also set after a hardware reset (re- set# asserted) or a power-up reset. the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. successful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting re- set#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit back to a 1 . if the password mode locking bit is not set, indicating persistent sector protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set command. once set the only means for clearing the ppb lock bit is by issuing a hard- ware or power-up reset. the password unlock command is ignored in persistent sector protection mode. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. in additi on, the following hardware data protection mea- sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal erase/program circuits are disabled, and the device resets. subs equent writes are ignored until v cc is greater than v lko . the
38 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce#, or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero (v il ) while oe# is a logical one (v ih ). power-up write inhibit if we# = ce# = v il and oe# = v ih during power-up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. v cc and v io power-up and power-down sequencing the device imposes no restrictions on v cc and v io power-up or power-down sequencing. assert- ing reset# to v il is required during the entire v cc and v io power sequence until the respective supplies reach the operating voltages. once, v cc and v io attain the operating voltages, de-asser- tion of reset# to v ih is permitted.
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 39 preliminary common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software inter- rogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-indepen- dent, and forward- and backward-c ompatible for the specified flash device families. flash vendors can standardize existing interfaces for long-term compatibility. this device enters the cfi query mode when th e system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 13?16. to ter- minate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 13?16. the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.spansion.com . alternatively, contact an amd representa- tive for copies of these documents. ta b l e 3 6 . cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string qry 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 37. cfi system interface string addresses data description 1bh 0023h v cc min. (write/erase) dq7?dq4: volts, dq3?dq0: 100 millivolt 1ch 0027h v cc max. (write/erase) dq7?dq4: volts, dq3?dq0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single word/doubleword program 2 n s 20h 0000h typical timeout for min. size buffer program 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for word/doubleword program 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0007h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
40 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary * on 16 mb device, data at address 31h is 1dh. ta b l e 3 8 . device geometry definition addresses data description 27h 0016h device size = 2 n byte 28h 29h 0005h 0000h flash device interface description (for complete description, please refer to cfi publication 100) 0000 = x8-only asynchronous interface 0001 = x16-only asynchronous interface 0002 = supports x8 and x16 via byte# with asynchronous interface 0003 = x 32-only asynchronous interface 0005 = supports x16 and x32 via wo rd# with asynchronous interface 2ah 2bh 0000h 0000h max. number of byte in multi-byte program = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 003dh* 0000h 0000h 0001h erase block region 2 information (refer to the cfi specification or cfi publication 100) 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100)
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 41 preliminary ta b l e 3 9 . cfi primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major version number, ascii (reflects modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h 0004h address sensitive unlock (dq1, dq0) 00 = required, 01 = not required silicon revision number (dq5?dq2 0000 = cs49 0001 = cs59 0010 = cs99 0011 = cs69 0100 = cs119 46h 0002h erase suspend (1 byte) 00 = not supported 01 = to read only 02 = to read and write 47h 0001h sector protect (1 byte) 00 = not supported, x = number of sectors in per group 48h 0000h temporary sector unprotect 00h = not supported, 01h = supported 49h 0006h sector protect/unprotect scheme (1 byte) 01 =29f040 mode, 02 = 29f016 mode 03 = 29f400 mode, 04 = 29lv800 mode 05 = 29bds640 mode (softw are command locking) 06 = bdd160 mode (new sector protect) 07 = 29lv800 + pdl128 (new sector protect) mode 4ah 0037h simultaneous read/write (1 byte) 00h = not supported, x = number of sectors in all banks except bank 1 4bh 0001h burst mode type 00h = not supported, 01h = supported 4ch 0000h page mode type 00h = not supported, 01h = 4 word page, 02h = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported (dq7-dq4: volt in hex, dq3-dq0: 100 mv in bcd) 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, (dq7-dq4: volt in hex, dq3-dq0: 100 mv in bcd) 4fh 0001h top/bottom boot sector flag (1 byte) 00h = uniform device, no wp# control, 01h = 8 x 8 kb sectors at top and bottom with wp# control 02h = bottom boot device 03h = top boot device 04h = uniform, bottom wp# protect 05h = uniform, top wp# protect if the number of erase block regi ons = 1, then ignore this field 50h 0001h program suspend 00 = not supported 01 = supported 51h 0000h write buffer size 2 (n+1) word(s) 57h 0002h bank organization (1 byte) 00 = if data at 4ah is zero xx = number of banks 58h 0017h bank 1 region information (1 byte) xx = number of sectors in bank 1 59h 0037h bank 2 region information (1 byte) xx = number of sectors in bank 2 5ah 0000h bank 3 region information (1 byte) xx = number of sectors in bank 3 5bh 0000h bank 4 region information (1 byte) xx = number of sectors in bank 4
42 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 41 on page 54 and table 42 on page 55 define the valid register com- mand sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. see ac characteristics on page 67 for timing diagrams. reading array data in non-burst mode the device is automatically set to reading arra y data after device po wer-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embed- ded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard re ad timings, except that if it reads at an ad- dress within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see sector erase and program suspend command on page 47 for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see ppb lock bit set command on page 51 . asynchronous read operation (non-burst) on page 27 for more information. see sector erase and program resume command on page 49 for more information on this mode. reading array data in burst mode the device is capable of very fast burst mode read operations. the configuration register sets the read configuration, burst order, freq uency configuration, and burst length. upon power on, the device defaults to the asynch ronous mode. in this mode, clk, and adv# are ignored. the device operates like a conventional flash device. data is available t acc /t ce nanosec- onds after address becomes stable, ce# become asserted. the device enters the burst mode by enabling synchronous burst reads in the configur ation register. the device exits burst mode by disabling synchronous burst reads in the configuration register. (see command definitions on page 42 ). the reset# command does not terminate the burst mode. system reset (power on reset) terminates the burst mode. the device has the regular control pins, i.e. chip enable (ce#), write en able (we#), and output enable (oe#) to control normal read and write operations. moreover, three additional control pins were added to allow easy interface with minimal glue logic to a wide range of microprocessors / microcontrollers for high performance burst read capability. these additi onal pins are address valid (adv#) and clock (clk). ce#, oe#, and we# are asynchronous (relative to clk). the burst mode read operation is a synchronous operation tied to the edge of the clock. the microprocessor / microcontroller supplies only the initial addre ss, all subsequent addresses are automatically generated by the device with a timing defined by the configuration register definition. the burst read cycle consists of an address phase and a corresponding data phase. during the address phase, the address valid (adv#) pin is asserted (taken low) for one clock period. together with the edge of the clk, the st arting burst address is loaded into the internal burst address counter. the internal burst address co unter can be configured to either 2, 4, and 8 double word linear burst, with or without wrap around. see initial access delay configuration on page 33 .
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 43 preliminary during the data phase, the first burst data is available after the initial access time delay defined in the configuration register. for subsequent burst data, every rising (or falling) edge of the clk triggers the output data with the burst output delay and sequence defined in the configuration register. table 41 on page 54 and table 42 on page 55 show all the commands executed by the device. the device automatically powers up in the read/reset state. it is not necessary to issue a read/ reset command after power-up or hardware reset. read/reset command after power-up or hardware reset, the device automatically enter the read state. it is not neces- sary to issue the reset command after power-up or hardware reset. standard microprocessor cycles retrieve array data, however, after power-up, only asynchronous accesses are permitted since the configuration register is at it s reset state with burst accesses disabled. the reset command is executed when the user needs to exit any of the other user command se- quences (such as autoselect, program, chip erase, etc.) to return to reading array data. there is no latency between executing the reset command and reading array data. the reset command does not disable the secured silicon sector if it is enabled. this function is only accomplished by issuing the secured silicon sector exit command. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacturer and device codes must be a ccessible while the device resides in the target system. prom programmers typically access the signature codes by raising a9 to v id . however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom program- ming methodology. the operation is initiated by writing the autoselect command sequence into the command register. th e bank address (ba) is latched du ring the autoselect command se- quence write operation to distinguish which bank the autoselect command references. reading the other bank after the autoselect command is written results in reading array data from the other bank and the specified address. following the command write, a read cycle from address (ba)xx00h retrieves the manufacturer code of (b a)xx01h. three sequential read cycles at ad- dresses (ba) xx01h, (ba) xx0eh, and (ba) xx0 fh read the three-byte device id (see ta b l e 4 1 ). (the autoselect command requires the user to execute the read/reset command to return the device back to reading the array contents.) program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writ- ing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. table 41 on page 54 and table 42 on page 55 show the address and data requirements for the program command sequence. during the embedded program algorithm, the sy stem can determine the status of the program operation by using dq7, dq6, or ry/by#. (see write operation status on page 56 for informa- tion on these status bits.) when the embedded program algorithm is complete, the device returns to reading array data and addresses are no longer latched. note that an address change is re- quired to begin read valid array data. except for program suspend, any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the programming
44 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary operation. the command sequence should be reinit iated once that bank returns to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be pro- grammed from a 0 back to a 1 . attempting to do so may halt the operation and set dq5 to 1 , or cause the data# polling algorithm to indicate the operation was successful. however, a suc- ceeding read shows that the data is still 0 . only erase operations can convert a 0 to a 1 . accelerated pr ogram command the accelerated chip program mode is designed to improve the word or double word program- ming speed. improving the programming speed is accomplished by using the acc pin to supply both the wordline voltage and the bitline current instead of using the v pp pump and drain pump, which is limited to 2.5 ma. because the external a cc pin is capable of supplying significantly large amounts of current compared to the drain pump, all 32 bits are available for programming with a single programming pulse. this is an enormous improvement over the standard 5-bit program- ming. if the user is able to supply an external power supply and connect it to the acc pin, significant time savings are realized. in order to enter the accelerated program mode, the acc pin must first be taken to v hh (12 v 0.5 v) and followed by the one-cycle command with the program address and data to follow. the accelerated chip program command is only executed when the device is in unlock bypass mode and during normal read/reset operating mode. in this mode, the write protection function is bypassed unless the ppb lock bit = 1. the accelerated program command is not permitted if the secured silicon sector is enabled. unlock bypass co mmand sequence the unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass pro- gram command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the pro- gram address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 39 on page 41 and table 41 on page 54 show the require- ments for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset com- mands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycles . the device then returns to reading array data. figure 4 on page 45 illustrates the algorithm for the program operation. see erase/program operations on page 73 for parameters, and to figure 21 on page 74 and figure 22 on page 74 for timing diagrams.
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 45 preliminary note: see table 41 and table 42 for program command sequence. figure 4. program operation unlock bypass entry command the unlock bypass command, once issued, is used to bypass the unlock sequence for program, chip erase, and cfi commands. this feature perm its slow prom programmers to significantly im- prove programming/erase throughput since the co mmand sequence often requires microseconds to execute a single write operation. therefore, on ce the unlock bypass command is issued, only the two-cycle program and erase bypass commands are required. the unlock bypass command is ignored if the secured silicon sector is enabled. to return back to normal operation, the unlock bypass reset command must be issued. the following four sections describe the commands that may be executed within the unlock by- pass mode. unlock bypass program command the unlock bypass program command is a two-cycle command that consists of the actual pro- gram command (a0h) and the program address/ data combination. this command does not require the two-cycle unlock sequence since the unlock bypass command was previously issued. as with the standard program command, multiple unlock bypass program commands can be is- sued once the unlock bypass command is issued. to return back to standard read operations, the unlock bypass reset command must be issued. the unlock bypass program command is ignored if the secured silicon sector is enabled. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
46 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary unlock bypass chip erase command the unlock bypass chip erase command is a 2-cycle command that consists of the erase setup command (80h) and the actual chip erase command (10h). this command does not require the two-cycle unlock sequence since the unlock bypass command was previously issued. unlike the standard erase command, there is no unlock bypass erase suspend or erase resume commands. to return back to standard read operations, the unlock bypass reset command must be issued. the unlock bypass program command is ignored if the secured silicon sector is enabled. unlock bypass cfi command the unlock bypass cfi command is available for prom programmers and target systems to read the cfi codes while in unlock bypass mode. see common flash interface (cfi) command on page 50 for specific cfi codes. to return back to standard read operations, the unlock bypass reset command must be issued. the unlock bypass program command is ignored if the secured silicon sector is enabled. unlock bypass reset command the unlock bypass reset command places the device in standard read/reset operating mode. once executed, normal read operations and user command sequences are available for execution. the unlock bypass program command is ignored if the secured silicon sector is enabled. chip erase command the chip erase command is used to erase the entire flash memory contents of the chip by issuing a single command. chip erase is a six-bus cycle operation. there are two unlock write cycles, fol- lowed by writing the erase set-up command. two more unlock write cycles are followed by the chip erase command. chip erase does not erase protected sectors. the chip erase operation initiates the embedded erase algorithm, which automatically prepro- grams and verifies the entire memory to an all zero pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. note that a hardware reset immediately terminates the programming operation. the command sequence should be reinitiated once that bank returns to read ing array data, to ensure data integrity. the embedded erase algorithm eras e begins on the rising edge of the last we# or ce# pulse (whichever occurs first) in the command sequence. the status of the erase operation is deter- mined three ways: ? data# polling of the dq7 pin (see dq7: data# polling on page 56 ) ? checking the status of the toggle bit dq6 (see dq6: toggle bit i on page 58 ) ? checking the status of the ry/by# pin (see ry/by#: ready/busy# on page 56 ) once erasure begins, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data, and addresses are no longer latched. note that an address change is required to begin read valid array data. figure 5 on page 48 illustrates the embedded erase algorithm. see the erase/program operations on page 73 for parameters, and figure 21 and figure 22 for timing diagrams. sector erase command the sector erase command is used to erase individual sectors or the entire flash memory con- tents. sector erase is a six-bus cycle operation. there are two unlock write cycles, followed by writing the erase set-up command. two more unlock write cycles are then followed by the erase command (30h). the sector address (any address location within the desired sector) is latched
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 47 preliminary on the falling edge of we# or ce# (whichever occurs last) while the command (30h) is latched on the rising edge of we# or ce# (whichever occurs first). specifying multiple sectors for erase is accomplished by writing the six bus cycle operation, as described above, and then followin g it by additional writes of on ly the last cycl e of the sector erase command to addresses or other sectors to be erased. the time between sector erase com- mand writes must be less than 80 s, otherwise the command is rejected. it is recommended that processor interrupts be disabled during this time to guarantee this critical timing condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 80 s from the rising edge of the last we# (or ce#) initiates the execution of the sector erase com- mand(s). if another falling edge of the we# (or ce#) occurs within the 80 s time-out window, the timer is reset. once the 80 s window time s out and erasure begins, only the erase suspend command is recognized (see sector erase and pr ogram suspend command on page 47 and sector erase and program resume command on page 49 ). if that occurs, the sector erase com- mand sequence should be reinitiated once that bank returns to reading array data, to ensure data integrity. loading the sector erase registers may be done in any sequence and with any number of sectors. sector erase does not require the user to progra m the device prior to erase. the device automat- ically preprograms all memory loca tions, within sectors to be eras ed, prior to electrical erase. when erasing a sector or sectors, the remaining unselected sectors or the write protected sectors are unaffected. the system is not required to provide any controls or timings during sector erase operations. the erase suspend and erase resume commands may be written as often as required during a sector erase operation. automatic sector erase operations begin on the ri sing edge of the we# or ce# pulse of the last sector erase command issued, and once the 80 s time-out window expires. the status of the sector erase operation is determined three ways: ? data# polling of the dq7 pin ? checking the status of the toggle bit dq6 ? checking the status of the ry/by# pin further status of device activity during the sect or erase operation is determined using toggle bit dq2 (see dq2: toggle bit ii on page 58 ). when the embedded erase algorithm is complete, the device returns to reading array data, and addresses are no longer latched. note that an address change is required to begin read valid array data. figure 5 on page 48 illustrates the embedded? erase algorithm, using a typical command se- quence and bus operation. see the erase/program operations on page 73 for parameters, and to figure 21 and figure 22 for timing diagrams. sector erase and program suspend command the sector erase and program suspend command allo ws the user to interrupt a sector erase or program operation and perform data read or programs in a sector that is not being erased or to the sector where a programming operation was initiated. this command is applicable only during the sector erase and programmin g operation, which includes the time-out period for sector erase. sector erase and program suspend operation mechanics the sector erase and program suspend command is ignored if writte n during the execution of the chip erase operation or embedded program algorithm (but resets the chip if written improperly during the command sequences). writing the se ctor erase and program command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. once in erase suspend, the de vice is available for reading (note that in the
48 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary notes: 1.see table 41 and table 42 for erase command sequence. 2. see dq3: sector erase timer for more information. figure 5. erase operation erase suspend mode, the reset command is not required for read operations and is ignored) or program operations in sectors not being erased. any other command written during the erase suspend mode is ignored, except for the sector erase and program resume command. writing the erase and program resume command resumes the sector erase operation. the bank address of the erase suspended bank is re quired when writing this command if the sector erase and program suspend command is written during a programming operation, the device suspends programming operations and al lows only read operations in sectors not se- lected for programming. further nesting of eith er erase or programming operations is not permitted. ta b l e 4 0 summarizes permissible operations du ring erase and program suspend. (a busy sector is one that is selected for programming or erasure.): when the sector erase and program suspend command is written during a sector erase opera- tion, the chip takes between 0.1 s and 20 s to actually suspend the operation and go into the erase suspended read mode (pseudo-read mode), at which time the user can read or program from a sector that is not erase suspended. reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that were not erase suspended. polling dq6 on two immediately consecutive reads from a given address provides the system with the ability to determine if the device is in erase or program suspend. before the device enters erase or program suspend, the dq6 pin toggles between two immediately consecutive reads from the same address. after the device enters erase suspend, dq6 stops toggling between two im- ta b l e 4 0 . allowed operations during erase/program suspend sector program suspend erase suspend busy sector program resume erase resume non-busy sectors read only read or program start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 49 preliminary mediately consecutive reads to the same address. during the sector erase operation and also in erase suspend mode, two immediately consecutive readings from the erase-suspended sector causes dq2 to toggle. dq2 does not toggle if reading from a non-busy (non-erasing) sector (stored data is read). no bits are toggled during program susp end mode. software must keep track of the fact that the device is in a suspended mode. after entering the erase-suspend-read mode, the system may read or program within any non- suspended sector: ? a read operation from the erase-suspended bank returns polling data during the first 8 s after the erase suspend command is issued; read operations thereafter return array data. read operations from the other bank return array data with no latency. ? a program operation while in the erase suspen d mode is the same as programming in the regular program mode, except that the data mu st be programmed to a sector that is not erase suspended. write operation status is obtained in the same manner as a normal pro - gram operation. sector erase and program resume command the sector erase and program resume command (30h) resumes a sector erase or program op- eration that was suspended. any further writ es of the sector erase and program resume command ignored. however, another sector erase and program suspend command can be writ- ten after the device resumes sector erase operations. note that until a suspended program or erase operation resumes, the contents of that sector are unknown. the sector erase and program resume command is ignored if the secured silicon sector is enabled. configuration register read command the configuration register read command is used to verify the contents of the configuration reg- ister. execution of this command is only allowed while in user mode and is not available during unlock bypass mode or during security mode. the configuration register read command is pre- ceded by the standard two-cycle unlock sequence, followed by the configuration register read command (c6h), and finally followed by performing a read operation to the bank address speci- fied when the c6h command was written. readin g the other bank results in reading the flash memory contents. the contents of the configurat ion register are place on dq15?dq0. contents of dq31?dq16 are xxxxh and should be ignored. the user should execute the read/reset com- mand to place the device back in standard us er operation after exec uting the configuration register read command. the configuration register read command is fully operational if the secured silicon sector is enabled. configuration register write command the configuration register write command is used to modify the contents of the configuration register. execution of this command is only allowed while in user mode and is not available during unlock bypass mode or during security mode. the configuration register write command is pre- ceded by the standard two-cycle unlock sequence, followed by the configuration register write command (d0h), and finally followed by writing the contents of the configuration register to any address. the contents of the configuration regi ster are placed on dq31?dq0. the contents of dq31?dq16 are xxxxh and are ignored. writing th e configuration register while an embedded algorithm? or erase suspend modes are executing results in the contents of the configuration register not being updated. the configuration register read command is fully operational if the secured silicon sector is enabled.
50 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary common flash interfa ce (cfi) command the common flash interface (cfi) command provides device size, geometry, and capability in- formation directly to the users system. flash devices that support cfi, have a query command that returns information about the device to the system. the query structure contents are read at the specific address locations following a single system write cycle where: ? a 98h query command code is written to 55h address location within the device?s address space ? the device is initially in any valid read state, such as read array or read id data other device statistics may exist within a long sequence of commands or data input; such se- quences must first be completed or terminated before writing of the 98h query command, otherwise invalid query data structure output may result. note that for data bus bits greater than dq7 (dq31?dq8), the valid query access code contains all zeroes ( 0 s) in the upper dq bus locations. thus, the 16-bit query command code is 0098h and the 32-bit query command code is 00000098h. to terminate the cfi operation, it is necessary to execute the read/reset command. the cfi command is not permitted if the secured silicon sector is enabled and simultaneous read/write operation is disabled once the command is entered. see common flash interface (cfi) command on page 50 for the specific cfi command codes. password program command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. depending upon the state of the word# pin, multiple password program commands are required. for a x32 bit data bus, 2 password program commands are required. the user must enter the unlock cycle, password pro- gram command (38h) and the prog ram address/data fo r each portion of the password when programming. there are no provisions for entering the 2-cycle unlock cycle, the password pro- gram command, and all the password data. there is no special addressing order required for programming the password. also, when the password is undergoing programming, simultaneous read/write operation is disabled. read operations to any memory location returns the program- ming status. once programming is complete, the user must is sue a read/reset command to return the device to normal operation. once the password is written and verified, the password mode locking bit must be set in order to prevent verification. the password program command is only capable of programming 0 s. programming a 1 after a cell is programmed as a 0 results in a time-out by the embedded program algo rithm? with the cell remaining as a 0 . the password is all f?s when shipped from the factory. all 64-b it password combinations are valid as a password. password programming is permitted if the secured silicon sector is enabled. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is pro- grammed and the user attempts to verify the password, the device always drives all f?s onto the dq data bus. the password verify command is permitted if the secured silicon sector is enabled. also, simul- taneous read/write operation is disabled when th e password verify command is executed. only the password is returned regardless of the bank ad dress. the lower two address bits (a0:a-1) are valid during the password verify. writing the read/reset command returns the device back to nor- mal operation.
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 51 preliminary password protection mode locking bit program command the password protection mode locking bit prog ram command programs the password protection mode locking bit, which prevents further verifies or updates to the password. once programmed, the password protection mode locking bit cannot be erased! if the password protection mode locking bit is verified as program without margin, the password protection mode locking bit pro- gram command can be executed to improve the program margin. once the password protection mode locking bit is programmed, the persistent sector protection locking bit program circuitry is disabled, thereby forcing the device to remain in the password protection mode. exiting the mode locking bit program command is accomplished by writing the read/reset command. the password protection mode locking bit program command is permitted if the secured silicon sector is enabled. persistent sector protection mo de locking bit program command the persistent sector protection mode lockin g bit program command programs the persistent sector protection mode locking bit, which prev ents the password mode locking bit from ever being programmed. if the persiste nt sector protection mode lo cking bit is verified as pro- grammed without margin, the persistent sector protection mode locking bit program command should be reissued to improve program margin. by disabling the program circuitry of the pass- word mode locking bit, the device is forced to remain in the persistent sector protection mode of operation, once this bit is set. exiting the persistent protection mode locking bit program com- mand is accomplished by writing the read/reset command. the persistent sector protection mode locking bit program command is permitted if the secured silicon sector is enabled. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear com- mand. once the ppb lock bit is set, it cannot be cleared unless the device is taken through a power-on clear or the password unlock command is executed. upon setting the ppb lock bit, the ppbs are latched into the dybs. if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on rese t cycle. exiting the ppb lock bit set command is accomplished by writing the read/reset command. the ppb lock bit set command is permitted if the secured silicon sector is enabled. dyb w rite c om ma nd the dyb write command is used to set or clear a dyb for a given sector. the high order address bits (a19?a11) are issued at the same time as the code 01h or 00h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dybs are modifiable at any time, re- gardless of the state of the ppb or ppb lock bit. the dybs are cleared at power-up or hardware reset. exiting the dyb write command is accomplished by writing the read/reset command. the dyb write command is permitted if the secured silicon sector is enabled. password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become accessible for modification. the exact pass- word must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 2 s at a time to prevent a ha cker from running through the all 64-bit combina- tions in an attempt to correctly match a passwor d. if the command is issued before the 2 s execution window for each portion of the unlock, the command is ignored.
52 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary the password unlock function is accomplished by writing password unlock command and data to the device to perform the clearing of the ppb lock bit. the password is 64 bits long, so the user must write the password unlock command 2 times for a x32 bit data bus. a0 is used to determine whether the 32 bit data quantity is used to matc h the upper 32 bits or lower 32 bits. writing the password unlock command is address order specific. in other words, for the x32 data bus config- uration, the lower 32 bits of the password are wr itten first and then the upper 32 bits of the password are written. writing out of sequence results in the password unlock not returning a match with the password and the ppb lock bit remains set. once the password unlock command is entered, the ry/by# pin goes low indicating that the device is busy. also, reading the small bank (25% bank) results in the dq6 pin toggling, indicating that the password unlock function is in progress. reading the large bank (75% bank) returns ac- tual array data. approximately 1usec is required for each portion of the unlock. once the first portion of the password unlock completes (ry/by# is not driven and dq6 does not toggle when read), the password unlock command is issued again, only this time with the next part of the password. the second password unlock command is the final command before the ppb lock bit is cleared (assuming a valid password). as with the first password unlock command, the ry/by# signal goes low and reading the device results in the dq6 pin toggling on successive read oper- ations until complete. it is the responsibility of the microprocessor to keep track of the number of password unlock commands (2 for x32 bus), the order, and when to read the ppb lock bit to confirm successful password unlock the password unlock command is permitted if the secured silicon sector is enabled. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually pro- grammed (but is bulk erased with the other pp bs). the specific sector address (a19?a11) are written at the same time as the program command 60h with a6 = 0. if the ppb lock bit is set and the corresponding ppb is set for the sector, the ppb program command does not execute and the command times-out without programming the ppb. the host system must determine whether a ppb is fully programmed by noting the status of dq0 in the sixth cycle of the ppb program command. if dq0 = 0, the entire six-cycle ppb program command sequence must be reissued until dq0 = 1. all ppb erase command the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually erasing a specific ppb. unlike the ppb program, no specific sector address is required. however, when the ppb erase command is written (60h) and a6 = 1, all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command does not execute and the command times- out without erasing the ppbs. the host system mu st determine whether all ppb was fully erased by noting the status of dq0 in the sixth cycle of the all ppb erase command. if dq0 = 1, the entire six-cycle all ppb erase command sequence must be reissued until dq0 = 1. it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase com- mand. if the user attempts to erase a cleared ppb, over-erasure may occur making it difficult to program the ppb at a later time. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. the all ppb erase command is permitted if the secured silicon sector is enabled. dyb w rite the dyb write command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, th e sector is protected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases.
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 53 preliminary since this is a volatile bit, removing power or resetting the device clears the dybs. the bank ad- dress is latched when the command is written. the dyb write command is permitted if the secured silicon sector is enabled. ppb lock bit set the ppb lock bit set command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sector is protected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device clears the dybs. the bank address is latched when the command is written. the ppb lock command is permitted if the secured silicon sector is enabled. dyb s ta tu s the programming of the dyb for a given sector can be verified by writing a dyb status verify com- mand to the device. ppb status the programming of the ppb for a given sector can be verified by writing a ppb status verify com- mand to the device. ppb lock bit status the programming of the ppb lock bit for a given se ctor can be verified by writing a ppb lock bit status verify command to the device. non-volatile protection bit program and erase flow the device uses a standard command sequence for programming or erasing the secured silicon sector protection, password locking, persistent se ctor protection mode locking, or persistent pro- tection bits. unlike devices that have the single high voltage sector unprotect/protect feature, the device has the standard two-cycle unlock follow ed by 60h, which places the device into non- volatile bit program or erase mode. once the mode is entered, the specific non-volatile bit status is read on dq0. figure 4 on page 45 shows a typical flow for programming the non-volatile bit and figure 5 on page 48 shows a typical flow for erasing the non-volatile bits. the secured silicon sector protection, password locking, persistent sector protection mode locking bits are not erasable after they are programmed. however, the ppbs are both erasable and programmable (depending upon device security). unlike single high voltage sector protect/unprotect, the a6 pin no longer functions as the pro- gram/erase selector nor the program/erase margin enable. instead, this function is accomplished by issuing the specific command for ei ther program (68h) or erase (60h). in asynchronous mode, the dq6 toggle bit indicates whether the program or erase sequence is active. (in synchronous mode, adv# indicates the st atus.) if the dq6 toggle bit toggles with ei- ther oe# or ce#, the non-volatile bit program or erase operation is in progress. when dq6 stops toggling, the value of the non-volatile bit is available on dq0.
54 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary ta b l e 4 1 . memory array command definitions command (notes) cycles bus cycles (notes 1?4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read ( 5 ) 1 ra rd reset ( 6 ) 1 xxx f0 autoselect ( 7 ) manufacturer id 4 555 aa 2aa 55 555 90 ba+x00 01 device id ( 11 ) 6 555 aa 2aa 55 555 90 ba+x01 7e ba+x0e 09 for 32 mb 36 or 08 for 16 mb ba+x0f 00/01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend ( 12 ) 1 ba b0 program/erase resume ( 13 ) 1 ba 30 cfi query ( 14 , 15 ) 1 55 98 accelerated program ( 16 ) 2 xx a0 pa pd configuration register verify ( 15 ) 3 555 aa 2aa 55 ba+555 c6 ba+xx rd configuration register write ( 17 ) 4 555 aa 2aa 55 555 d0 xx wd unlock bypass entry ( 18 ) 3 555 aa 2aa 55 555 20 unlock bypass program ( 18 ) 2 xx a0 pa pd unlock bypass erase ( 18 ) 2 xx 80 xx 10 unlock bypass cfi ( 14 , 18 ) 1 xx 98 unlock bypass reset ( 18 ) 2 xx 90 xx 00 legend: ba = bank address. the set of addresses that comprise a bank. the system may write any address within a bank to identify that bank for a command. pa = program address (amax?a0). addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data (dqmax?dq0) written to location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. ra = read address (amax?a0). rd = read data. data dqmax?dq0 at address location ra. sa = sector address. the set of addresses that comprise a sector. the system may write any address within a sector to identify that sector for a command. wd = write data. see configuration register on page 31 definition for specific write data. data latched on rising edge of we#. x = don?t care notes: 1. see table 27 on page 23 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote re ad cycles. all other cycles are write operations. 4. during unlock cycles, (lower address bits are 555 or 2aah as shown in table) address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autosele ct mode, or if dq5 goes high (while the bank is provid ing status information). 7. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the manufacturer id or device id information. see autoselect command on page 43 for more information. 8. this command cannot be executed until the unlock bypass command must be executed before writing this command sequence. the unlock bypass reset command must be executed to return to normal operation. 9. this command is ignored during any embedded program, erase or suspended operation. 10. valid read operations include asynchronous and burst read mode operations. 11. the device id must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates ordering option 00, 01h indicates ordering option 01. 12. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the program/erase suspend mode. the program/erase susp end command is valid only during a sector erase operation, and requires the bank address. 13. the program/erase resume command is valid only during the erase suspend mode, and requires the bank address. 14. command is valid when device is ready to read array data or when device is in autoselect mode. 15. asynchronous read operations. 16. acc must be at v id during the entire operation of this command. 17. command is ignored during any embedded program, embedded erase, or suspend operation. 18. the unlock bypass entry command is required prior to any unlock bypass operation. the unlock bypass reset command is required to return to the read mode.
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 55 preliminary ta b l e 4 2 . sector protection command definitions command (notes) cycles bus cycles (notes 1 ? 4 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secured silicon sector entry 3 555 aa 2aa 55 555 88 secured silicon sector exit 4 555 aa 2aa 55 555 90 xx 00 secured silicon protection bit status 6 555 aa 2aa 55 555 60 ow rd(0) password program ( 5 , 7 , 8 ) 4 555 aa 2aa 55 555 38 pwa[0-1] pwd[0-1] password verify 4 555 aa 2aa 55 555 c8 pwa[0-1] pwd[0-1] password unlock ( 7 , 8 ) 5 555 aa 2aa 55 555 28 pwa[0-1] pwd[0-1] ppb program ( 5 , 6 ) 6 555 aa 2aa 55 555 60 sg+wp 68 sg+wp 48 sg+wp rd(0) all ppb erase ( 5 , 9 , 10 ) 6 555 aa 2aa 55 555 60 wp 60 wp 40 wp rd(0) ppb status ( 11 , 12 ) 4 555 aa 2aa 55 ba+555 90 sa+x02 00/01 ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status 4 555 aa 2aa 55 ba+555 58 sa rd(1) dyb write ( 7 ) 4 555 aa 2aa 55 555 48 sa x1 dyb erase ( 7 ) 4 555 aa 2aa 55 555 48 sa x0 dyb status ( 12 ) 4 555 aa 2aa 55 ba+555 58 sa rd(0) ppmlb program ( 5 , 6 ) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status ( 5 ) 6 555 aa 2aa 55 555 60 pl rd(0) spmlb program ( 5 , 6 ) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status ( 5 ) 6 555 aa 2aa 55 555 60 sl rd(0) legend: dyb = dynamic protection bit ow = address (a5?a0) is (011x10). ppb = persistent protection bit pwa = password address. a0 selects between the low and high 32-bit portions of the 64-bit password pwd = password data. must be written over two cycles. pl = password protection mode lock address (a5?a0) is (001x10) rd(0) = read data dq0 protection indi cator bit. if protected, dq0= 1, if unprotected, dq0 = 0. rd(1) = read data dq1 protection indicator bit. if protected, dq1 = 1, if unprotected, dq1 = 0. sa = sector address. the set of addresses that comprise a sector. the system may write any address within a sector to identify that sector for a command. sg = sector group address ba = bank address. the set of addresses that comprise a bank. the system may write any address within a bank to identify that bank for a command. sl = persistent protection mode lock address (a5?a0) is (010x10) wp = ppb address (a5?a0) is (111010) x = don?t care ppmlb = password protec tion mode locking bit spmlb = persistent protection mode locking bit notes: 1. see table 27 on page 23 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock cycles, (lower address bits are 555 or 2aah as shown in table) address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. the reset command returns the device to reading the array. 6. the fourth cycle programs the addressed locking bit. the fifth and sixth cycles are used to validate whether the bit is fully programmed. if dq0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 7. data is latched on the rising edge of we#. 8. the entire four bus-cycle sequence must be entered for each portion of the password. 9. the fourth cycle erases all ppbs. the fifth and sixth cycles are used to validate whether the bits were fully erased. if dq0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 10. before issuing the erase command, all ppbs should be programmed in order to prevent over-erasure of ppbs. 11. in the fourth cycle, 00h indicates ppb set; 01h indicates ppb not set. 12. the status of additional ppbs and dybs may be read (following the fourth cycle) without reissuing the entire command sequence.
56 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary write operation status the device provides several bits to determine the status of a write operation: dq2, dq3, dq5, dq6, dq7, and ry/by#. ta b l e 4 3 and the following subsections describe the functions of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the device features a data# polling flag as a method to indicate to the host system whether the embedded algorithms are in progress or are co mplete. during the embedded program algorithm, an attempt to read the bank in which programming was initiated produces the complement of the data last written to dq7. upon completion of the embedded program algorithm, an attempt to read the device produces the true last data wri tten to dq7. note that data# polling returns in- valid data for the address being programmed or erased. for example, the data read for an address programmed as 0000 0000 1000 0000b, returns xxxx xxxx 0xxx xxxxb during an embedded program op eration. once the em bedded program algo- rithm is complete, the true data is read back on dq7. note that at the instant when dq7 switches to true data, the other bits may not yet be true. ho wever, they are all true data on the next read from the device. please note that data# polling may give misleading status when an attempt is made to write to a protected sector. for chip erase, the data# polling flag is valid after the rising edge of the sixth we# pulse in the six write pulse sequence. for sector erase, the data# polling is valid after the last rising edge of the sector erase we# pulse. data# polling must be performed at sector addresses within any of the sectors being erased and not a sector that is a protected sector. otherwise, the status may not be valid. dq7 = 0 during an embedded erase algorithm (chip erase or sector erase operation), but returns a 1 after the operation completes because it drops back into read mode. in asynchronous mode, just prior to the completion of the embedded algorithm operations, dq7 may change asynchronously while oe# is assert ed low. (in synchronous mode, adv# exhibits this behavior.) the status information may be invalid during the instance of transition from status information to array (memory) data. an extra validity check is therefore specified in the data poll- ing algorithm. the valid array data on dq31?dq0 is available for reading on the next successive read attempt. the data# polling feature is only active during the embedded programming algorithm, embedded erase algorithm, erase suspend, erase suspend-program mode, or sector erase time-out. if the user attempts to write to a protected sector, data# polling is activated for about 1 s: the device then returns to read mode, with the data from the protected sector unchanged. if the user attempts to erase a protected sector, toggle bit (dq6) is activated for about 150 s; the device then returns to read mode, without having erased the protected sector. table 43 shows the outputs for data# polling on dq7. figure 6 on page 57 shows the data# poll- ing algorithm. figure 23 shows the timing diagram for synchronous status dq7 data polling. ry/by#: r ea dy /bu sy# the device provides a ry/by# open drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or completed. if the output is low, the device is busy with either a program, erase, or reset operation. if the output is floating, the device is ready to accept any read/write or erase operation. wh en the ry/by# pin is low, the device does not accept any additional program or erase commands with the exception of the erase suspend com- mand. if the device enters erase suspend mode, the ry/by# output is floating. for programming, the ry/by# is valid (ry/by# = 0) after the rising edge of the fourth we# pulse in the four write pulse sequence. for chip erase, the ry/by# is valid after the rising edge of the sixth we# pulse
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 57 preliminary in the six write pulse sequence. for sector erase, the ry/by# is also valid after the rising edge of the sixth we# pulse. notes: 1. va = valid address for programming. during a sector erase op eration, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5 figure 6. data# polling algorithm if reset# is asserted during a program or erase operation, the ry/by# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is floating ), the reset operation is completed in a time of t ready (not during embedded algo- rithms). the system can read data t rh after the reset# pin returns to v ih . since the ry/by# pin is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . an external pull-up resistor is required to take ry/by# to a v ih level since the output is an open drain. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
58 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary table 43 shows the outputs for ry/by#. figures 15 , 19 , and 21 show ry/by# for read, reset, pro- gram, and erase operations, respectively. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorith m operation, two immediately consecutive read cycles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. for asynchronous mode, either oe# or ce# can be used to control the read cycles. for synchro- nous mode, the rising edge of adv# is used or the rising edge of clock while adv# is low. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to dete rmine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog- gling. however, the system must also use dq2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use dq7 (see dq7: data# polling on page 56 ). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling once the embed- ded program algorithm is complete. table 43 shows the outputs for toggle bit i on dq6. figure 7 shows the toggle bit algorithm in flowchart form, and reading toggle bits dq6/dq2 on page 59 explains the algorithm. figure 24 shows the toggle bit timing diagrams. figure 24 shows the differences between dq2 and dq6 in graphical form. also see dq2: toggle bit ii on page 58 . figure 24 shows the timing diagram for synchronous toggle bit status. dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system performs two immediately consecutive reads at addresses within those sectors that were selected for erasure. (for asynchronous mode, either oe# or ce# can be used to control the read cycles. for synchronous mode, adv# is used.) but dq2 cannot distin- guish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sec- tors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 4 3 to compare outputs for dq2 and dq6. toggle bit algorithm in is shown in figure 7 in flowchart form, and the algorithm is explained in reading toggle bits dq6/dq2 on page 59 . also see dq6: toggle bit i on page 58 . figure 24 shows the toggle bit timing diagram. figure 25 shows the differences between dq2 and dq6 in graphical form. figure 26 shows the timing diagram for synchronous dq2 toggle bit status.
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 59 preliminary reading toggle bits dq6/dq2 refer to figure 24 for the following discussion. whenever the system initially begins reading tog- gle bit status, it must perform two immediatel y consecutive reads of dq7?dq0 to determine whether a toggle bit is toggling. typically, the sy stem would note and store the value of the toggle bit after the first read. after th e second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is no t toggling, the device completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two immediately consecutive read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see dq5: exceeded timing limits on page 60 ). if it is, the system should then determine again whether the toggle bit is toggling, since the togg le bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through suc- cessive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 7 ).
60 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary notes: 1. read toggle bit with two immediately consecutive reads to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1 . figure 7. toggle bit algorithm dq5: exceeded timing limits dq5 indicates whether the program or erase time exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 . this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a 1 to a location that is pre- viously programmed to 0 . only an erase operation can change a 0 back to a 1 . under this condition, the device halts the operation, and wh en the operation exceeds the timing limits, dq5 produces a 1 . under both these conditions, the system must issue the reset command to return the device to reading array data. start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq0-dq7) address = va dq6 = toggle? read byte twice (dq 0-dq7) adrdess = va read byte (dq0-dq7) address = va fail pass (note 1) (notes 1 , 2 )
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 61 preliminary dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation started. (the sector erase timer does not apply to the chip erase com- mand.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from 0 to 1 . the system may ignore dq3 if the system can guarantee that the time between additional sector erase commands is always less than 50 s. also see sector erase command on page 46 . after the sector erase command sequence is writte n, the system should read the status on dq7 (data# polling) or dq6 (toggle bit i) to ensure the device accepted the command sequence, and then read dq3. if dq3 is 1 , the internally controlled erase cycle started; all further commands (other than erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device accepts additional sector erase commands. to ensure the command is accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 4 3 shows the outputs for dq3. notes: 1. dq5 switches to 1 when an embedded program or embedded erase operation exceeds the maximum timing limits. see dq5: exceeded timing limits for more information. 2. dq7 and dq2 require a valid address when reading status information. see dq7: data# polling and dq2: toggle bit ii for further details. ta b l e 4 3 . write operation status operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# to g g l e 0 n/a no toggle 0 embedded erase algorithm 0 to g g l e 0 1 to g g l e 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a to g g l e 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# to g g l e 0 n/a n/a 0
62 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +145c v cc , v io ( note 1 , note 5 ) . . . . . . . . . . . . . -0.5 v to + 3.0v (16mb), -0.5v to + 2.75v (32mb) acc, a9 , oe# , and reset# ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +13.0 v address, data, control signals except clk ( note 1 , note 6 ) . . . . . . . . . . . . -0.5v to 3.6v (16 mb), ?0.5 v to 2.75 v (32 mb) all other pins ( note 1 , note 6 ). . . . . . . . . . . . -0.5v to 3.6v (16 mb),?0.5 v to 2.75 v (32 mb) output short circuit current ( note 3 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input at i/o pins may overshoot v ss to -2.0v for periods of up to 20 ns. see figure 9 . maximum dc voltage on output and i/o pins is 3.6v (16mb), 2.75v (32mb). during voltage transitions output pins may overshoot to v cc + 2.0v for periods up to 20 ns. see figure 9 . 2. minimum dc input voltage on pins acc, a9, oe#, and rese t# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot v ss to -2.0v for periods of up to 20 ns. see figure 8 . maximum dc input voltage on pin a9 and oe# is +13.0 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum ra ting conditions for extended periods may affe ct device reliability. 5. parameter describes v io power supply. 6. parameter describes i/o pin voltage tolerances. figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 63 preliminary operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +125c v cc supply voltages v cc for 2.6 v regulated voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.50 v to 2.75 v v io supply voltages v io . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65 v to 3.6 v (16 mb), 1.65 v to 2.75 v (32 mb) note: operating ranges define those limits between which the functionality of the device is guaranteed.
64 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary dc characteristics cmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component. 2. i cc active while embedded erase or embedded program is in progress. 3. not 100% tested. 4. maximum i cc specifications are tested with v cc = v ccmax . parameter description test conditions min typ max unit i li input load current v in = v ss to v io , v io = v io max 1.0 a i liwp wp# input load current v in = v ss to v io , v io = v io max ?25 i lit a9, acc input load current v cc = v ccmax ; a9 = 12.5 v 35 i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 i ccb v cc active burst read current ( 1 ) ce# = v il , oe# = v il 56 mhz 8 double word 70 90 ma 66, 75 mhz i cc1 v cc active asynchronous read current ( 1 ) ce# = v il , oe# = v il 1 mhz 10 i cc3 v cc active program current ( 2 , 4 ) ce# = v il , oe# = v ih , acc = v ih 40 50 i cc4 v cc active erase current ( 2 , 4 ) ce# = v il , oe# = v ih , acc = v ih 20 50 i cc5 v cc standby current (cmos) v cc = v cc max , ce# = v cc 0.3 v 60 a i cc6 v cc active current (read while write) ce# = v il , oe# = v il 30 90 ma i cc7 v cc reset current () reset# = v il 60 a i cc8 automatic sleep mode current v ih = v cc 0.3 v, v il = v ss 0.3 v 60 a i acc v acc acceleration current acc = v hh 20 ma v il input low voltage ?0.5 0.3 x v io v v ih input high voltage 0.7 x v io v cc v ilclk clk input low voltage ?0.2 0.3 x v io v ihclk clk input high voltage 0.7 x v cc 2.75 v id voltage for autoselect v cc = 2.5 v 11.5 12.5 v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 i olrb ry/by#, output low current v ol = 0.4 v 8 ma v hh accelerated (acc pin) high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 x v cc v v oh output high voltage i oh = ?100 a, v cc = v cc min v io ?0.1 v lko low v cc lock-out voltage ( 3 ) 1.6 2.0
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 65 preliminary dc characteristics zero power flash note: addresses are switching at 1 mhz figure 10. i cc1 current vs. time (showing acti ve and automatic sleep currents) figure 11. typical i cc1 vs. frequency 0 500 1000 1500 2000 2500 3000 3500 4000 0 1 2 3 4 time in ns supply current in ma 2.7 v 1234 5 0 1 2 3 4 5 frequency in mhz supply current in ma
66 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary test conditions note: diodes are in3064 or equivalent figure 12. te s t s e t u p test specifications key to switching waveforms switching waveforms figure 13. input waveforms and measurement levels ta b l e 4 4 . test specifications test condition 40 mhz, 56 mhz 66 mhz, 75mhz unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0 v ? v io v input timing measurement reference levels v io /2 output timing measurement reference levels v io /2 waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) c l device under te s t v io v ss v io /2 v v io /2 v output measurement level input
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 67 preliminary ac characteristics v cc and v io power-up figure 14. v cc and v io power-up diagram parameter description test setup speed unit t vcs v cc setup time min 50 s t vios v io setup time t rsth reset# low hold time v cc v iop reset# t vcs t rsth t vios
68 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary ac characteristics asynchronous read operations notes: 1. not 100% tested. 2. see figure 12 and table 44 for test specifications figure 15. conventional read operations timings parameter description test setup speed options unit jedec std. 75 mhz, 0r 66 mhz, 0p 56 mhz, 0m 40 mhz, oj t avav t rc read cycle time (note 1) min 48 54 64 67 ns t avqv t acc address to output delay ce# = v il oe# = v il max 48 54 64 67 t elqv t ce chip enable to output delay oe# = v il max 52 58 69 71 t glqv t oe output enable to output delay max 20 28 t ehqz t df chip enable to output high z note 1 max 10 t ghqz t df output enable to output high z note 1 min 2 max 10 t oeh output enable hold time note 1 read min 0 toggle and data# polling min 10 t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first note 1 min 2 t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 69 preliminary ac characteristics burst mode read for 32 mb & 16 mb note: not 100% tested. parameter description speed options unit jede c std. 75 mhz, 0r 32 mhz 66 mhz, 0p 56 mhz, 0m 40 mhz, oj t bacc burst access time valid clock to output delay max 7.5 fbga 9 fbga 9.5 pqfp 10 fbga 10 pqfp 17 ns t advcs adv# setup time to rising edge of clk min 5.75 6 t advch adv# hold time from rising edge of clk min 1.5 2 t advp adv# pulse width (32mb, 75mhz) min 12 13 15 22 t dvch valid data hold from clk ( note note: ) min 2 3 t dind clk to valid ind/wait# max 7.5 fbga 9 fbga 9.5 pqfp 10 fbga 10 pqfp 17 t indh ind/wait# hold from clk min 2 3 t iacc clk to valid data out, initial burst access max 48 54 64 67 t clk clk period min 13. 15 18 25 max 60 t clkr clk rise time max 3 t clkf clk fall time max 3 t ckl clk low time min 2 2.5 3 t clkh clk to high time min 2 2.5 3 t ces ce# setup time to clock min 6 t ch ce# hold time min 16 mb =3 32 mb = 8 t acs address setup time to clk min 6 t ach address hold time from adv# rising edge of clk while adv# is low min 5 t oe output enable to output valid max 20 28 t df t oez output enable to output high z ( note note: ) min 2 2 3 3 max 7.5 10 15 17 t ehqz t cez chip enable to output high z ( note note: ) max 7.5 10 15 17 t wadvh we hold time after adv falling edge min 0 t wcks we rising edge setup time to clock rising edge min 5
70 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary ac characteristics figure 16. burst mode read figure 17. asynchronous command write timing note: all commands have the same number of cycles in both asynchronous and synchronous modes, including the read/ reset command. only a single array access occurs after the f0h command is entered. all subsequent accesses are burst mode when the burst mode option is enabled in the configuration register. da da + 2 da + 3 da + 31 oe#* data addresses aa ind# adv# clk ce# t ces t acs t advcs t advch t ach t oe t bacc t dvch t oez t cez t iacc da + 1 adv# ce# valid data addresses data we# oe# ind/wait# clk stable address t cs t ch t as t ah t oeh t ds t dh t wph t wc
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 71 preliminary ac characteristics figure 18. synchronous command write/read timing note: all commands have the same number of cycles in both asynchronous and synchronous modes, including the read/ reset command. only a single array access occurs after the f0h command is entered. all subsequent accesses are burst mode when the burst mode option is enabled in the configuration register. hardware reset (reset#) note: not 100% tested. parameter description test setup all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read or write (see note) max 11 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns t as clk adv# data in addresses data oe# data out valid address we# ind/wait# ce# valid address t ds t wp t ces t advp t advcs t wcks t oe t acs t ach t acs t df t ehqz t dh t wadvh t advch 10 ns t ach t wc
72 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary ac characteristics figure 19. reset# timings figure 20. wp# timing reset# ry/by# ry/by# t rp t ready reset timing to bank not executing embedded algorithm t ready ce#, oe# t rh ce#, oe# reset timing to bank executing embedded algorithm reset# t rp t rb program/erase command wp# data valid wp# t ch t ds t dh we# ry/by# t wpws t wprh t wp
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 73 preliminary ac characteristics erase/program operations notes: 1. not 100% tested. 2. see command definitions for more information. note: pa = program address, pd = program data, d out is the true data at the program address. parameter description all speed options jedec std. unit t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 t wlax t ah address hold time min 25 t dvwh t ds data setup to we# rising edge min 18 t whdx t dh data hold from we# rising edge min 2 t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 t elwl t cs ce# setup time min 0 t wheh t ch ce# hold time min 2 t wlwh t wp we# width min 25 t whwl t wph write pulse width high min 30 t whwh1 t whwh1 programming operation (note 2) double-word ty p 18 s t whwh2 t whwh2 sector erase operation (note 2) ty p 1.0 sec. t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# min 0 ns t busy ry/by# delay after we# rising edge max 90 t wpws wp# setup to we# rising edge with command min 20 t wprh wp# hold after ry/by# rising edge min 2 oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs statu d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa
74 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary ac characteristics note: sa = sector address (for sector erase), va = valid address for reading status data ( see write operation status ). figure 21. chip/sector erase operation timings figure 22. back-to-back cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t wph
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 75 preliminary ac characteristics note: va = valid address. illustration shows first status cycle af ter command sequence, last status read cycle, and array data read cycle. figure 23. data# polling timings (during embedded algorithms) note: va = valid address; not required for dq6. illustration show s first two status cycle after command sequence, last sta - tus read cycle, and array data read cycle. figure 24. toggle bit timings (durin g embedded algorithms) we# ce# oe# high z t oe high z dq7 data ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc t wc we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va
76 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary ac characteristics note: the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. figure 25. dq2 vs. dq6 for erase/er ase suspend operations notes: 1. the timings are similar to synchronous read timings and asynchronous data polling timings/toggle bit timing. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete, the toggle bits stop toggling. 3. rdy is active with data (a18 = 0 in the configuration regi ster). when a18 = 1 in the configuration register, rdy is active one clock cycle before data. 4. data polling requires burst access time delay. figure 26. synchronous data polling timing/toggle bit timings we# dq6 dq2 enter embedded erasing erase suspend enter erase suspend program erase resume erase erase suspend read erase suspend program erase suspend read erase erase complete ce# clk avd# addresses oe# data rdy status data status data va va t oe t oe
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 77 preliminary ac characteristics * valid address for sector protect: a[7:0] = 3ah. valid address for sector unprotect: a[7:0] = 3ah. ** command for sector protect is 68h. command for sector unprotect is 60h. *** command for sector protect verify is 48h. command for sector unprotect verify is 40h. figure 27. sector protect/unprotect timing diagram alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see command definitions for more information. parameter description all speed options unit jedec std. t avav t wc write cycle time (note 1) min 65 ns t avel t as address setup time min 0 t elax t ah address hold time min 45 t dveh t ds data setup time min 35 t ehdx t dh data hold time min 2 t oes output enable setup time min 0 t ghel t ghel read recovery time before write (oe# high to we# low) min t wlel t ws we# setup time min t ehwh t wh we# hold time min t wp we# width min 32 t eleh t cp ce# pulse width min 16 t ehel t cph ce# pulse width high min 30 t whwsh1 t whwh1 programming operation (note 2) double-word typ 18 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec. sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h/68h** 40h/48h*** valid* valid* valid* status sector protect/unprotect verify v ih
78 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary ac characteristics notes: 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last two bus cycles of the command sequence. figure 28. alternate ce# controlled write operation timings t ghel t ws oe# ce# we# reset# t ds data t ah t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy t wph t wp addresses
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 79 preliminary erase and programming performance notes: 1. typical program and erase times as sume the following conditions: 25 c, 2.5 v v cc , 100k cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 145c, v cc = 2.5 v, 1m cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 41 and table 42 for further information on command definitions. 6. ppbs have a program/erase cycle endurance of 100 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. pqfp and fortified bga pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 1.0 5 s excludes 00h programming prior to erasure (note 4) chip erase time 16 mb = 46 32 mb = 78 16 mb = 230 32 mb = 460 s double word program time 18 250 s excludes system level overhead (note 5) accelerated do uble word program time 8 130 s accelerated chip program time 16 mb = 5 32 mb = 10 16 mb = 50 32 mb = 100 s chip program time (note 3) x32 16 mb = 12 32 mb = 24 16 mb = 120 32 mb = 240 s description min max input voltage with respect to v ss on all pins except i/o pins (including a9, acc, and wp#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf
80 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary revision summary s29cd016g revision history revision a1 (march 22, 2004) performance characteristics burst mode read: changed to 66-mhz. ordering information changed device number/description ca ll out to show the two 16-mbit configurations. table 12 and table 13 corrected which sectors report to which bank. asynchronous read operations table removed the or speed option. revision a2 (may 24, 2004) ?spansion? logo replaces amd in bullet seven, first column. fujitsu mbm29lv and mbm129f added to bullet ten, first column. ultra low power co nsumption bullet ?capable of...? deleted from first bullet, second column. block diagram reset# moved, ry/by added. simultaneous read/write circuit block diagram ry/by added; bank 1 added; bank 0 added. pin configuration ?a pull-up resistor of 10k...? added to ry/by#. ordering information additional ordering options updated to ?protects sectors 44 and 45?. device number/description bit description altered. simultaneous read/write op eration with zero latency table 3 and 4 bank # change. auto select mode table 5: manufacturer id row updated (a3, a2). table 5: dq7 to dq0 column updated.
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 81 preliminary linear burst read operations table 6: ?(x16)? removed from header row. ind/wait# operation in linear mode figure 2 - ?address 2? removed. initial burst access delay control figure 3 - valid address line changed. notes - clock cycles updated. configuration register table 9: cr14 reserve bit assigned asd. table 9: speed options changed. table 10: cr14 reserve changed to asd. table12. sector addresse s for ordering option 00 bank changed to 0. bank changed to 1. table 13. sector addresses for ordering option 01 bank changed to 0. bank changed to 1. table 16. device geometry definition 0005 = supports x16 and x32 via word#...? removed. unlock bypass command sequence table ?18? replaced with ?19? in text. table 19. memory array comma nd definitions (x32 mode) autoselect (7) - device id (11); fifth/data changed to ?36?. table 20. sector protection co mmand definitions (x32 mode) pbb status (11,12) third/addr changed to ?sg?. ppb lock bit status; third/addr ?ba? removed. dyb status; third/addr changed to ?sa?. absolute maximum ratings address, data... changed to 3.6v. table 22 cmos compatible input high voltage max changed to 3.6. ry/by#, output low current min re- moved, max added (8). table 23. test specifications test conditions changed to oj,om,op. ac characteristics figure 14 updated reset#.
82 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary table number 24. asynchronous read operations om speed options; output enable to output delay ?20? added. table 26. hardware reset last row deleted. erase/program operations twadvh row added. twcks row added. table 27. alternate ce# controlled erase/program operations twph row added, twadvh row added, twcks row added. physical dimensions latchup characteristics deleted. pin description ?wait# provides data valid feedback only when the burst length is set to continuous.? removed from document. revision a3 (may 26, 2004) block diagram on page 6 moved reset# to point to the state control/command register. figure 2, on page 22 updated note added ?double-word? to figure title. table 9, ?configuration register definitions,? on page 24 added ?cr14 = automatic sleep mode...? configurations. table 1, ?sector addresses for orde ring option 00,? on page 33 re-inserted previously missing data. removed ?note 1? from sector sa1. added ?note 3? to sector sa44 and sa45. moved sectors sa15 - sa30 to bank 1. table on page 35 added ?note 3? to sector sa45. revision a4 (november 5, 2004) global added reference links added colophon updated trademark product selector guide removed note from product selector guide table
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 83 preliminary block diagram changed text on input/output buffers to show dq0 to dq31 pin configuration changed text in acc description accelerated program and erase operations changed text in this paragraph table 5 change address text column. secsi sector entry command changed address text in this paragraph figure 18 changed time spec call out from 10 ns to t wadvh2 table 27 added new row for t wadvh2 rev history family data sheet rev a (july 18, 2005) global merged s29cd016g and s29cd032g datashee ts into one family cd-g datasheet changed datasheet status to "preliminary information" added in 75mhz parameters ordering information model numbers (character 15th & 16th) changed to reflect mask revision, autoselect code and top/bottom boot added gt grade under temperature range and quality grade added note to "refer to the kgd datasheet supplement for die/wafer sales" product selector guide changed min. initial clock delay values memory map and sector protect groups modified notes 1 & 3 add in note 4 simultaneous read /write operation removed table 2: bank assignment for boot bank sector deivice removed table 3: ordering option 00 removed table 4: ordering option 01 secured silicon sector added in electronic marking
84 s29cd-g flash family s29cd-g_00_b0 november 14, 2005 preliminary common flash memory interface updated website to reflect spansion.com changed address 28h from 0003h to 0005h command definitions remove secured silicon protection bit program command absolute maximum ratings changed overshoot/undershoot to be 0.7v from 2.0v changed address, data, control si gnals to -0.5v to 3v for 16mb operating ranges changed vio to 1.65v to 3.6v burst mode read for 32mb & 16 mb changed tadvcs = 5.75ns for 75mhz changed tadvch to be 2ns for 66mhz, 56mhz, 40 mhz changed tiacc values rounded tclk values changed tcr to tclkr changed tcf to tclkf changed tcl to tclkl changed tch to tclkh and changed values removed tds, tdh, tas, tah, tcs added twadvh, twcks erase/program operations removed twcks alternative ce# controlled erase/program operations added twadvh added twcks rev history family datasheet rev b0 (november 14, 2005) absolute maximum ratings changed under/overshoot to 2.0v changed vcc, vio values changed address, data, control signal values note 5 & 6 revision history added in previous revision histories. erase/program operations added note 1 to twc and tvcs
november 14, 2005 s29cd-g_00_b0 s29cd-g flash family 85 preliminary global changed secsi to secured silicon. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, deve loped and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuclear reaction control in nucle ar facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men - tioned uses of the products. any semiconductor device has an inherent chance of failure. you must protect against injury, damag e or loss from such failures by incorporating safety design measures in to your facility and equipment such as redu ndancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior au - thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty , express, implied, or stat utory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2004-2005 spansion llc. all righ ts reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion l lc. other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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